PIC18LF27J53-I/ML Microchip Technology, PIC18LF27J53-I/ML Datasheet - Page 139

• Manufacturer Part Number: PIC18LF27J53-I/ML
• Description: IC PIC MCU 128KB FLASH 28QFN
• Manufacturer: Microchip Technology
• Series: PIC® XLP™ 18Fr

Specifications of PIC18LF27J53-I/ML

• Core Size: 8-Bit
• Program Memory Size: 128KB (64K x 16)
• Core Processor: PIC
• Speed: 48MHz
• Connectivity: I²C, LIN, SPI, UART/USART, USB
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 22
• Program Memory Type: FLASH
• Ram Size: 3.8K x 8
• Voltage - Supply (vcc/vdd): 2 V ~ 2.75 V
• Data Converters: A/D 10x10b/12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Controller Family/series: PIC18
• Cpu Speed: 48MHz
• Digital Ic Case Style: QFN
• Supply Voltage Range: 1.8V To 3.6V
• Embedded Interface Type: I2C, SPI, USART
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant

9.5
The RCON register contains bits used to determine the
cause of the last Reset or wake-up from Idle or Sleep
mode. RCON also contains the bit that enables
interrupt priorities (IPEN).
REGISTER 9-19:
 2010 Microchip Technology Inc.
bit 7
Legend:
R = Readable bit
-n = Value at POR
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
R/W-0
IPEN
RCON Register
IPEN: Interrupt Priority Enable bit
1 = Enable priority levels on interrupts
0 = Disable priority levels on interrupts (PIC16CXXX Compatibility mode)
Unimplemented: Read as ‘0’
CM: Configuration Mismatch Flag bit
For details on bit operation, see Register 5-1.
RI: RESET Instruction Flag bit
For details on bit operation, see Register 5-1.
TO: Watchdog Timer Time-out Flag bit
For details on bit operation, see Register 5-1.
PD: Power-Down Detection Flag bit
For details on bit operation, see Register 5-1.
POR: Power-on Reset Status bit
For details on bit operation, see Register 5-1.
BOR: Brown-out Reset Status bit
For details on bit operation, see Register 5-1.
U-0
—
RCON: RESET CONTROL REGISTER (ACCESS FD0h)
W = Writable bit
‘1’ = Bit is set
R/W-1
CM
R/W-1
RI
Preliminary
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
PIC18F47J53 FAMILY
R-1
TO
R-1
PD
x = Bit is unknown
R/W-0
POR
DS39964B-page 139
R/W-0
BOR
bit 0