PIC18LF27J53-I/ML Microchip Technology, PIC18LF27J53-I/ML Datasheet - Page 168

• Manufacturer Part Number: PIC18LF27J53-I/ML
• Description: IC PIC MCU 128KB FLASH 28QFN
• Manufacturer: Microchip Technology
• Series: PIC® XLP™ 18Fr

Specifications of PIC18LF27J53-I/ML

• Core Size: 8-Bit
• Program Memory Size: 128KB (64K x 16)
• Core Processor: PIC
• Speed: 48MHz
• Connectivity: I²C, LIN, SPI, UART/USART, USB
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 22
• Program Memory Type: FLASH
• Ram Size: 3.8K x 8
• Voltage - Supply (vcc/vdd): 2 V ~ 2.75 V
• Data Converters: A/D 10x10b/12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Controller Family/series: PIC18
• Cpu Speed: 48MHz
• Digital Ic Case Style: QFN
• Supply Voltage Range: 1.8V To 3.6V
• Embedded Interface Type: I2C, SPI, USART
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant

PIC18F47J53 FAMILY
REGISTER 10-14: RPINR12: PERIPHERAL PIN SELECT INPUT REGISTER 12 (BANKED EF2h)
REGISTER 10-15: RPINR13: PERIPHERAL PIN SELECT INPUT REGISTER 13 (BANKED EF3h)
REGISTER 10-16: RPINR14: PERIPHERAL PIN SELECT INPUT REGISTER 14 (BANKED EF4h)
DS39964B-page 168
bit 7
Legend:
R = Readable bit
-n = Value at POR
bit 7-5
bit 4-0
bit 7
Legend:
R = Readable bit
-n = Value at POR
bit 7-5
bit 4-0
bit 7
Legend:
R = Readable bit
-n = Value at POR
bit 7-5
bit 4-0
U-0
U-0
U-0
—
—
—
Unimplemented: Read as ‘0’
T1GR<4:0>: Timer1 Gate Input (T1G) to the Corresponding RPn Pin bits
Unimplemented: Read as ‘0’
T3GR<4:0>: Timer3 Gate Input (T3G) to the Corresponding RPn Pin bits
Unimplemented: Read as ‘0’
T5GR<4:0>: Timer5 Gate Input (T5G) to the Corresponding RPn Pin bits
U-0
U-0
U-0
—
—
—
R/W = Readable bit, Writable bit if IOLOCK = 0
W = Writable bit
R/W = Readable bit, Writable bit if IOLOCK = 0
W = Writable bit
R/W = Readable bit, Writable bit if IOLOCK = 0
W = Writable bit
‘1’ = Bit is set
‘1’ = Bit is set
‘1’ = Bit is set
U-0
U-0
U-0
—
—
—
T1GR4
T3GR4
T5GR4
R/W-1
R/W-1
R/W-1
Preliminary
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
T1GR3
T3GR3
T5GR3
R/W-1
R/W-1
R/W-1
T1GR2
T3GR2
T5GR2
R/W-1
R/W-1
R/W-1
 2010 Microchip Technology Inc.
x = Bit is unknown
x = Bit is unknown
x = Bit is unknown
T1GR1
T3GR1
T5GR1
R/W-1
R/W-1
R/W-1
T1GR0
T3GR0
T5GR0
R/W-1
R/W-1
R/W-1
bit 0
bit 0
bit 0