DS72011RB120FPV Renesas Electronics America, DS72011RB120FPV Datasheet - Page 1191

• Manufacturer Part Number: DS72011RB120FPV
• Description: IC SH7201 MPU ROMLESS 176LQFP
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7200r

Specifications of DS72011RB120FPV

• Core Size: 32-Bit
• Core Processor: SH-2A
• Speed: 120MHz
• Connectivity: CAN, EBI/EMI, FIFO, I²C, SCI, Serial Sound
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 104
• Program Memory Type: ROMless
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 70°C
• Package / Case: 176-LQFP
• No. Of I/o's: 109
• Ram Memory Size: 32KB
• Cpu Speed: 120MHz
• Digital Ic Case Style: LQFP
• Supply Voltage Range: 3V To 3.6V
• Operating Temperature Range: -20°C To +70°C
• Embedded Interface Type: I2C, SSI
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: R0K572011S000BE - KIT STARTER FOR SH7201HS0005KCU11H - EMULATOR E10A-USB H8S(X),SH2(A)
• Eeprom Size: -
• Program Memory Size: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant

SH7201 Group
R01UH0026EJ0300 Rev. 3.00
Sep 24, 2010
5.1.2 Exception Handling
Operations
Table 5.2 Timing of Exception
Source Detection and Start of
Exception Handling
5.2.4 Manual Reset
(3) Notes at a Manual Reset
5.3.1 Address Error Sources
Table 5.7 Bus Cycles and
Address Errors
5.3.2 Address Error Exception
Handling
5.7.1 Types of Exceptions
Triggered by Instructions
Item
Page
93
100
101
102
108
Revision (See Manual for Details)
Table amended
Description deleted
... will be deferred until the CPU acquires the bus
mastership.
IBNR of the INTC are initialized by a manual reset.
Table amended
Note added
When an address error occurs, address error
exception handling starts after the bus cycle in which
the address error occurred ends* and execution of the
instruction being executed completes. The CPU
operates as follows. ...
Note: * In the case of address error related to data
Description amended
Exception handling can be triggered by trap
instructions, general illegal instructions, slot illegal
instructions, integer division exceptions, and FPU
exceptions, as shown in table 5.10.
Type
Data
read/write
Exception
Instructions
Bus Cycle
read/write. In the case of address error related
to instruction fetch, if the bus cycle in which
the address error occurred doesn't end until
the entire three above-mentioned operations
end, the CPU will start address error
exception handling again until the bus cycle in
which the address error occurred ends.
Bus
Master
CPU
Source
Integer division
exceptions
FPU exceptions
Bus Cycle Description
Longword data accessed from other than
a long-word boundary
Double longword data accessed from
double longword boundary
Double longword data accessed from
other than double longword boundary
Byte or word data accessed in on-chip
peripheral module space*
Timing of Source Detection and Start of Handling
Starts when detecting division-by-zero exception or overflow
exception caused by division of the negative maximum value
(H'80000000) by − 1.
Exception handling starts triggered by disabled operation
exception of floating-point operation instruction (IEEE754
standard), division exception by zero, overflow, underflow, or
imprecise exception. Setting the QIS bit in FPSCR or inputting
qNaN as well as ±∞ as the floating-point operation instruction
source also starts exception handling.
The CPU and the BN bit in
2
Main Revisions for This Edition
Address Errors
Address error occurs
None (normal)
Address error occurs
None (normal)
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