DS72011RB120FPV Renesas Electronics America, DS72011RB120FPV Datasheet - Page 836
![IC SH7201 MPU ROMLESS 176LQFP](/photos/28/61/286154/176-lqfp_sml.jpg)
DS72011RB120FPV
Manufacturer Part Number
DS72011RB120FPV
Description
IC SH7201 MPU ROMLESS 176LQFP
Manufacturer
Renesas Electronics America
Series
SuperH® SH7200r
Datasheet
1.R0K572011S000BE.pdf
(1222 pages)
Specifications of DS72011RB120FPV
Core Size
32-Bit
Core Processor
SH-2A
Speed
120MHz
Connectivity
CAN, EBI/EMI, FIFO, I²C, SCI, Serial Sound
Peripherals
DMA, POR, PWM, WDT
Number Of I /o
104
Program Memory Type
ROMless
Ram Size
32K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Data Converters
A/D 8x10b; D/A 2x8b
Oscillator Type
Internal
Operating Temperature
-20°C ~ 70°C
Package / Case
176-LQFP
No. Of I/o's
109
Ram Memory Size
32KB
Cpu Speed
120MHz
Digital Ic Case Style
LQFP
Supply Voltage Range
3V To 3.6V
Operating Temperature Range
-20°C To +70°C
Embedded Interface Type
I2C, SSI
Rohs Compliant
Yes
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
R0K572011S000BE - KIT STARTER FOR SH7201HS0005KCU11H - EMULATOR E10A-USB H8S(X),SH2(A)
Eeprom Size
-
Program Memory Size
-
Lead Free Status / RoHS Status
Lead free / RoHS Compliant, Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
DS72011RB120FPV
Manufacturer:
Renesas Electronics America
Quantity:
10 000
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- Download datasheet (8Mb)
SH7201 Group
Section 18 Serial Sound Interface (SSI)
18.4.7
Serial Bit Clock Control
This function is used to control and select which clock is used for the serial bus interface.
If the serial clock direction is set to input (SCKD = 0), the SSI module is in clock slave mode and
the shift register uses the bit clock that was input to the SSISCK pin.
If the serial clock direction is set to output (SCKD = 1), this module is in clock master mode, and
the shift register uses the oversampling clock or a divided oversampling clock as the bit clock. The
oversampling clock is divided by the ratio specified by the serial oversampling clock division ratio
bits (CKDV) in SSICR for use as the bit clock by the shift register.
In either case the module pin, SSISCK, is the same as the bit clock.
Page 808 of 1190
R01UH0026EJ0300 Rev. 3.00
Sep 24, 2010
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