DS72011RB120FPV Renesas Electronics America, DS72011RB120FPV Datasheet - Page 77

• Manufacturer Part Number: DS72011RB120FPV
• Description: IC SH7201 MPU ROMLESS 176LQFP
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7200r

Specifications of DS72011RB120FPV

• Core Size: 32-Bit
• Core Processor: SH-2A
• Speed: 120MHz
• Connectivity: CAN, EBI/EMI, FIFO, I²C, SCI, Serial Sound
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 104
• Program Memory Type: ROMless
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 70°C
• Package / Case: 176-LQFP
• No. Of I/o's: 109
• Ram Memory Size: 32KB
• Cpu Speed: 120MHz
• Digital Ic Case Style: LQFP
• Supply Voltage Range: 3V To 3.6V
• Operating Temperature Range: -20°C To +70°C
• Embedded Interface Type: I2C, SSI
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: R0K572011S000BE - KIT STARTER FOR SH7201HS0005KCU11H - EMULATOR E10A-USB H8S(X),SH2(A)
• Eeprom Size: -
• Program Memory Size: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant

SH7201 Group
R01UH0026EJ0300 Rev. 3.00
Sep 24, 2010
Instruction
CLIPS.B
CLIPS.W
CLIPU.B
CLIPU.W Rn
DIV1
DIV0S
DIV0U
DIVS
DIVU
DMULS.L Rm,Rn
DMULU.L Rm,Rn
DT
EXTS.B
EXTS.W
EXTU.B
Rn
Rn
Rn
Rm,Rn
Rm,Rn
R0,Rn
R0,Rn
Rn
Rm,Rn
Rm,Rn
Rm,Rn
Instruction Code
0100nnnn10010001
0100nnnn10010101
0100nnnn10000001
0100nnnn10000101
0011nnnnmmmm0100
0010nnnnmmmm0111
0000000000011001
0100nnnn10010100
0100nnnn10000100
0011nnnnmmmm1101
0011nnnnmmmm0101
0100nnnn00010000
0110nnnnmmmm1110
0110nnnnmmmm1111
0110nnnnmmmm1100
Operation
When Rn > (H'0000007F),
(H'0000007F) → Rn, 1 → CS
when Rn < (H'FFFFFF80),
(H'FFFFFF80) → Rn, 1 → CS
When Rn > (H'00007FFF),
(H'00007FFF) → Rn, 1 → CS
When Rn < (H'FFFF8000),
(H'FFFF8000) → Rn, 1 → CS
When Rn > (H'000000FF),
(H'000000FF) → Rn, 1 → CS
When Rn > (H'0000FFFF),
(H'0000FFFF) → Rn, 1 → CS
1-step division (Rn ÷ Rm)
MSB of Rn → Q,
MSB of Rm → M, M ^ Q → T
0 → M/Q/T
Signed operation of Rn ÷ R0
→ Rn 32 ÷ 32 → 32 bits
Unsigned operation of Rn ÷ R0
→ Rn 32 ÷ 32 → 32 bits
Signed operation of Rn × Rm
→ MACH, MACL
32 × 32 → 64 bits
Unsigned operation of Rn ×
Rm → MACH, MACL
32 × 32 → 64 bits
Rn – 1 → Rn
When Rn is 0, 1 → T
When Rn is not 0, 0 → T
Byte in Rm is
sign-extended → Rn
Word in Rm is
sign-extended → Rn
Byte in Rm is
zero-extended → Rn
Execu-
tion
Cycles
1
1
1
1
1
1
1
36
34
2
2
1
1
1
1
T Bit
⎯
⎯
⎯
⎯
Calcu-
lation
result
Calcu-
lation
result
0
⎯
⎯
⎯
⎯
Com-
parison
result
⎯
⎯
⎯
SH2,
SH2E SH4
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Compatibility
Page 49 of 1190
Section 2 CPU
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
SH-2A
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes