DS72011RB120FPV Renesas Electronics America, DS72011RB120FPV Datasheet - Page 807
![IC SH7201 MPU ROMLESS 176LQFP](/photos/28/61/286154/176-lqfp_sml.jpg)
DS72011RB120FPV
Manufacturer Part Number
DS72011RB120FPV
Description
IC SH7201 MPU ROMLESS 176LQFP
Manufacturer
Renesas Electronics America
Series
SuperH® SH7200r
Datasheet
1.R0K572011S000BE.pdf
(1222 pages)
Specifications of DS72011RB120FPV
Core Size
32-Bit
Core Processor
SH-2A
Speed
120MHz
Connectivity
CAN, EBI/EMI, FIFO, I²C, SCI, Serial Sound
Peripherals
DMA, POR, PWM, WDT
Number Of I /o
104
Program Memory Type
ROMless
Ram Size
32K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Data Converters
A/D 8x10b; D/A 2x8b
Oscillator Type
Internal
Operating Temperature
-20°C ~ 70°C
Package / Case
176-LQFP
No. Of I/o's
109
Ram Memory Size
32KB
Cpu Speed
120MHz
Digital Ic Case Style
LQFP
Supply Voltage Range
3V To 3.6V
Operating Temperature Range
-20°C To +70°C
Embedded Interface Type
I2C, SSI
Rohs Compliant
Yes
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
R0K572011S000BE - KIT STARTER FOR SH7201HS0005KCU11H - EMULATOR E10A-USB H8S(X),SH2(A)
Eeprom Size
-
Program Memory Size
-
Lead Free Status / RoHS Status
Lead free / RoHS Compliant, Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
DS72011RB120FPV
Manufacturer:
Renesas Electronics America
Quantity:
10 000
- Current page: 807 of 1222
- Download datasheet (8Mb)
SH7201 Group
R01UH0026EJ0300 Rev. 3.00
Sep 24, 2010
Bit
14
13
12
11
10
SCKP
SWSP
Bit Name
SWSD
SPDP
SDTA
Initial
Value
0
0
0
0
0
R/W
R/W
R/W
R/W
R/W
R/W
Description
Serial WS Direction
0: Serial word select is input, slave mode.
1: Serial word select is output, master mode.
Note: Only the following settings are allowed: (SCKD,
Serial Bit Clock Polarity
0: SSIWS and SSIDATA change at the SSISCK falling
1: SSIWS and SSIDATA change at the SSISCK rising
Serial WS Polarity
0: SSIWS is low for 1st channel, high for 2nd channel.
1: SSIWS is high for 1st channel, low for 2nd channel.
Serial Padding Polarity
0: Padding bits are low.
1: Padding bits are high.
Note: When MUEN = 1, padding bits are low. (The
Serial Data Alignment
0: Transmitting and receiving in the order of serial data
1: Transmitting and receiving in the order of padding
SSIDATA input sampling timing at
the time of reception (TRMD = 0)
SSIDATA output change timing at
the time of transmission (TRMD = 1)
SSIWS input sampling timing at
the time of slave mode (SWSD = 0)
SSIWS output change timing at
the time of master mode (SWSD = 1)
edge (sampled at the SCK rising edge).
edge (sampled at the SCK falling edge).
and padding bits
bits and serial data
SWSD) = (0,0) and (1,1). Other settings are
prohibited.
MUTE function is given priority.)
Section 18 Serial Sound Interface (SSI)
SCKP = 0
SSISCK rising
edge
SSISCK falling
edge
SSISCK rising
edge
SSISCK falling
edge
SCKP = 1
SSISCK falling
edge
SSISCK rising
edge
SSISCK falling
edge
SSISCK rising
edge
Page 779 of 1190
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