DS72011RB120FPV Renesas Electronics America, DS72011RB120FPV Datasheet - Page 15

• Manufacturer Part Number: DS72011RB120FPV
• Description: IC SH7201 MPU ROMLESS 176LQFP
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7200r

Specifications of DS72011RB120FPV

• Core Size: 32-Bit
• Core Processor: SH-2A
• Speed: 120MHz
• Connectivity: CAN, EBI/EMI, FIFO, I²C, SCI, Serial Sound
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 104
• Program Memory Type: ROMless
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 70°C
• Package / Case: 176-LQFP
• No. Of I/o's: 109
• Ram Memory Size: 32KB
• Cpu Speed: 120MHz
• Digital Ic Case Style: LQFP
• Supply Voltage Range: 3V To 3.6V
• Operating Temperature Range: -20°C To +70°C
• Embedded Interface Type: I2C, SSI
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: R0K572011S000BE - KIT STARTER FOR SH7201HS0005KCU11H - EMULATOR E10A-USB H8S(X),SH2(A)
• Eeprom Size: -
• Program Memory Size: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant

Section 11 Direct Memory Access Controller (DMAC) ...................................299
11.1
11.2
11.3
11.4
11.5
11.6
11.7
11.8
11.9
R01UH0026EJ0300 Rev. 3.00
Sep 24, 2010
Features............................................................................................................................. 299
Input/Output Pins.............................................................................................................. 301
Register Descriptions ........................................................................................................ 302
11.3.1
11.3.2
11.3.3
11.3.4
11.3.5
11.3.6
11.3.7
11.3.8
11.3.9
11.3.10 DMA Activation Control Register (DMSCNT)................................................ 332
11.3.11 DMA Interrupt Control Register (DMICNT).................................................... 333
11.3.12 DMA Common Interrupt Control Register (DMICNTA) ................................. 334
11.3.13 DMA Interrupt Status Register (DMISTS) ....................................................... 335
11.3.14 DMA Transfer End Detection Register (DMEDET) ........................................ 336
11.3.15 DMA Arbitration Status Register (DMASTS).................................................. 338
Operation .......................................................................................................................... 340
11.4.1
11.4.2
11.4.3
Completion of DMA Transfer and Interrupts ................................................................... 347
11.5.1
11.5.2
11.5.3
Suspending, Restarting, and Stopping of DMA Transfer ................................................. 352
11.6.1
11.6.2
DMA Requests.................................................................................................................. 353
11.7.1
11.7.2
11.7.3
Determining DMA Channel Priority................................................................................. 357
11.8.1
11.8.2
11.8.3
Units of Transfer and Positioning of Bytes for Transfer................................................... 360
DMA Current Source Address Register (DMCSADR) .................................... 306
DMA Current Destination Address Register (DMCDADR) ............................ 307
DMA Current Byte Count Register (DMCBCT) .............................................. 308
DMA Reload Source Address Register (DMRSADR) ..................................... 309
DMA Reload Destination Address Register (DMRDADR) ............................. 310
DMA Reload Byte Count Register (DMRBCT) ............................................... 311
DMA Mode Register (DMMOD) ..................................................................... 312
DMA Control Register A (DMCNTA) ............................................................. 318
DMA Control Register B (DMCNTB) ............................................................. 326
DMA Transfer Mode ........................................................................................ 340
DMA Transfer Condition.................................................................................. 342
DMA Activation ............................................................................................... 346
Completion of DMA Transfer........................................................................... 347
DMA Interrupt Requests................................................................................... 348
DMA End Signal Output .................................................................................. 350
Suspending and Restarting DMA Transfer ....................................................... 352
Stopping DMA Transfer on Any Channel ........................................................ 352
Sources of DMA Requests................................................................................ 353
Synchronous Circuits for DMA Request Signals.............................................. 353
Sense Mode for DMA Requests........................................................................ 354
Channel Priority Order...................................................................................... 357
Operation during Multiple DMA Requests....................................................... 357
Output of the DMA Acknowledge and DNA Active Signals ........................... 358
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