DS72011RB120FPV Renesas Electronics America, DS72011RB120FPV Datasheet - Page 408

• Manufacturer Part Number: DS72011RB120FPV
• Description: IC SH7201 MPU ROMLESS 176LQFP
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7200r

Specifications of DS72011RB120FPV

• Core Size: 32-Bit
• Core Processor: SH-2A
• Speed: 120MHz
• Connectivity: CAN, EBI/EMI, FIFO, I²C, SCI, Serial Sound
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 104
• Program Memory Type: ROMless
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 70°C
• Package / Case: 176-LQFP
• No. Of I/o's: 109
• Ram Memory Size: 32KB
• Cpu Speed: 120MHz
• Digital Ic Case Style: LQFP
• Supply Voltage Range: 3V To 3.6V
• Operating Temperature Range: -20°C To +70°C
• Embedded Interface Type: I2C, SSI
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: R0K572011S000BE - KIT STARTER FOR SH7201HS0005KCU11H - EMULATOR E10A-USB H8S(X),SH2(A)
• Eeprom Size: -
• Program Memory Size: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant

Section 12 Multi-Function Timer Pulse Unit 2 (MTU2)
12.3.1
The TCR registers are 8-bit readable/writable registers that control the TCNT operation for each
channel. The MTU2 has a total of eight TCR registers, one each for channels 0 to 4 and three
(TCRU_5, TCRV_5, and TCRW_5) for channel 5. TCR register settings should be conducted
only when TCNT operation is stopped.
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Bit
7 to 5
4, 3
2 to 0
Don't care
Bit Name
CCLR[2:0]
CKEG[1:0]
TPSC[2:0]
Timer Control Register (TCR)
Initial value:
Initial
Value
000
00
000
R/W:
Bit:
R/W
R/W
R/W
R/W
R/W
7
0
CCLR[2:0]
R/W
6
0
Description
Counter Clear 0 to 2
These bits select the TCNT counter clearing source.
See tables 12.4 and 12.5 for details.
These bits select the input clock edge. When the input
clock is counted using both edges, the input clock
period is halved (e.g. Pφ/4 both edges = Pφ/2 rising
edge). If phase counting mode is used on channels 1
and 2, this setting is ignored and the phase counting
mode setting has priority. Internal clock edge selection
is valid when the input clock is Pφ/4 or slower. When
Pφ/1, or the overflow/underflow of another channel is
selected for the input clock, although values can be
written, counter operation compiles with the initial value.
00: Count at rising edge
01: Count at falling edge
1x: Count at both edges
Time Prescaler 0 to 2
These bits select the TCNT counter clock. The clock
source can be selected independently for each channel.
See tables 12.6 to 12.10 for details.
Clock Edge 0 and 1
R/W
5
0
R/W
CKEG[1:0]
4
0
R/W
3
0
R/W
2
0
TPSC[2:0]
R/W
1
0
R/W
0
0
R01UH0026EJ0300 Rev. 3.00
SH7201 Group
Sep 24, 2010