DS72011RB120FPV Renesas Electronics America, DS72011RB120FPV Datasheet - Page 844
![IC SH7201 MPU ROMLESS 176LQFP](/photos/28/61/286154/176-lqfp_sml.jpg)
DS72011RB120FPV
Manufacturer Part Number
DS72011RB120FPV
Description
IC SH7201 MPU ROMLESS 176LQFP
Manufacturer
Renesas Electronics America
Series
SuperH® SH7200r
Datasheet
1.R0K572011S000BE.pdf
(1222 pages)
Specifications of DS72011RB120FPV
Core Size
32-Bit
Core Processor
SH-2A
Speed
120MHz
Connectivity
CAN, EBI/EMI, FIFO, I²C, SCI, Serial Sound
Peripherals
DMA, POR, PWM, WDT
Number Of I /o
104
Program Memory Type
ROMless
Ram Size
32K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Data Converters
A/D 8x10b; D/A 2x8b
Oscillator Type
Internal
Operating Temperature
-20°C ~ 70°C
Package / Case
176-LQFP
No. Of I/o's
109
Ram Memory Size
32KB
Cpu Speed
120MHz
Digital Ic Case Style
LQFP
Supply Voltage Range
3V To 3.6V
Operating Temperature Range
-20°C To +70°C
Embedded Interface Type
I2C, SSI
Rohs Compliant
Yes
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
R0K572011S000BE - KIT STARTER FOR SH7201HS0005KCU11H - EMULATOR E10A-USB H8S(X),SH2(A)
Eeprom Size
-
Program Memory Size
-
Lead Free Status / RoHS Status
Lead free / RoHS Compliant, Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
DS72011RB120FPV
Manufacturer:
Renesas Electronics America
Quantity:
10 000
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Section 19 Controller Area Network (RCAN-ET)
19.2.4
The diagram of the memory map is shown below.
Page 816 of 1190
H'000
H'002
H'004
H'006
H'008
H'00A
H'00C
H'020
H'022
H'02A
H'032
H'03A
H'042
H'04A
H'052
H'05A
Note: The locations not used (between H'000 and H'2F2) are reserved and cannot be accessed.
Addresses shown above are offset addrsses. As for actual addresses, see section 28, List of Registers.
Memory Map
Bit 15
Transmit Error Counter
Data Frame Receive Pending Register (RXPR0)
Unread Message Status Register (UMSR0)
Transmit Acknowledge Register (TXACK0)
Mailbox Interrupt Mask Register (MBIMR0)
Bit timing Configuration Register 1 (BCR1)
Bit timing Configuration Register 0 (BCR0)
Remote Frame Pending Register (RFPR0)
Abort Acknowledge Register (ABACK0)
Transmit Pending Register (TXPR1)
Transmit Pending Register (TXPR0)
Transmit Cancel Register (TXCR0)
Interrupt Request Register (IRR)
(TEC)
Master Control Register (MCR)
General Status Register(GSR)
Interrupt Mask Register (IMR)
Receive Error Counter
Figure 19.2 RCAN-ET Memory Map
(REC)
Bit 0
H'0A0
H'0A4
H'100
H'104
H'108
H'10A
H'10C
H'10E
H'110
H'120
H'140
H'160
H'2E0
Bit 15
Mailbox-0 Control 1 (NMC, MBC, DLC)
Mailbox-15 Control/LAFM/Data etc.
Mailbox-1 Control/LAFM/Data etc.
Mailbox-2 Control/LAFM/Data etc.
Mailbox-3 Control/LAFM/Data etc.
(STDID, EXTID, RTR, IDE)
0
2
4
6
Mailbox 0 Data (8 bytes)
Mailbox-0 Control 0
LAFM
R01UH0026EJ0300 Rev. 3.00
1
3
5
7
SH7201 Group
Sep 24, 2010
Bit 0
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