DS72011RB120FPV Renesas Electronics America, DS72011RB120FPV Datasheet - Page 315

• Manufacturer Part Number: DS72011RB120FPV
• Description: IC SH7201 MPU ROMLESS 176LQFP
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7200r

Specifications of DS72011RB120FPV

• Core Size: 32-Bit
• Core Processor: SH-2A
• Speed: 120MHz
• Connectivity: CAN, EBI/EMI, FIFO, I²C, SCI, Serial Sound
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 104
• Program Memory Type: ROMless
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 70°C
• Package / Case: 176-LQFP
• No. Of I/o's: 109
• Ram Memory Size: 32KB
• Cpu Speed: 120MHz
• Digital Ic Case Style: LQFP
• Supply Voltage Range: 3V To 3.6V
• Operating Temperature Range: -20°C To +70°C
• Embedded Interface Type: I2C, SSI
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: R0K572011S000BE - KIT STARTER FOR SH7201HS0005KCU11H - EMULATOR E10A-USB H8S(X),SH2(A)
• Eeprom Size: -
• Program Memory Size: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant

SH7201 Group
10.1.2
SYCBESTS1 indicates the status of slave bus (peripheral bus (1)) regarding whether a timeout
occurred, whether an illegal address access was made, or which bus master accessed the slave bus.
Table 10.2 shows the correspondence between the bus space and the slave bus.
R01UH0026EJ0300 Rev. 3.00
Sep 24, 2010
Bit
31 to 15 ⎯
14
13
12 to 10 ⎯
Initial value:
Initial value:
R/W:
R/W:
Bit:
Bit:
Bus Monitor Status Register 1 (SYCBESTS1)
Bit Name
PTO
PER
31
15
—
—
R
R
0
0
PTO
30
14
—
R
R
0
0
PER
29
13
—
R
R
0
0
Initial
Value
All 0
0
0
All 0
28
12
—
—
R
R
0
0
27
11
—
—
R
R
0
0
R/W
R
R
R
R
26
10
—
—
R
R
0
0
Description
Reserved
These bits are always read as 0. The write value
should always be 0.
Timeout
This bit indicates that a timeout occurred on peripheral
bus (1) when the first bus error occurred.
0: Timeout not generated
1: Timeout generated
Illegal Address Access
This bit indicates that an illegal address access was
made on peripheral bus (1) when the first bus error
occurred.
0: Illegal address access not made
1: Illegal address access made
Reserved
These bits are always read as 0. The write value
should always be 0.
PMST[1:0]
25
—
R
R
0
9
0
24
—
R
R
0
8
0
23
—
—
R
R
0
7
0
22
—
—
R
R
0
6
0
21
—
—
R
R
0
5
0
20
—
—
R
R
0
4
0
19
—
—
R
R
0
3
0
Section 10 Bus Monitor
18
—
—
R
R
0
2
0
Page 287 of 1190
17
—
—
R
R
0
1
0
16
—
—
R
R
0
0
0