DS72011RB120FPV Renesas Electronics America, DS72011RB120FPV Datasheet - Page 953

• Manufacturer Part Number: DS72011RB120FPV
• Description: IC SH7201 MPU ROMLESS 176LQFP
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7200r

Specifications of DS72011RB120FPV

• Core Size: 32-Bit
• Core Processor: SH-2A
• Speed: 120MHz
• Connectivity: CAN, EBI/EMI, FIFO, I²C, SCI, Serial Sound
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 104
• Program Memory Type: ROMless
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 70°C
• Package / Case: 176-LQFP
• No. Of I/o's: 109
• Ram Memory Size: 32KB
• Cpu Speed: 120MHz
• Digital Ic Case Style: LQFP
• Supply Voltage Range: 3V To 3.6V
• Operating Temperature Range: -20°C To +70°C
• Embedded Interface Type: I2C, SSI
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: R0K572011S000BE - KIT STARTER FOR SH7201HS0005KCU11H - EMULATOR E10A-USB H8S(X),SH2(A)
• Eeprom Size: -
• Program Memory Size: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant

SH7201 Group
22.6.2
PFDR is a 16-bit read-only register that stores the port F data. Bits PF7DR to PF0DR correspond
to pins PF7 to PF0, respectively.
If a pin is set to the general output function, the pin will output the value written to the
corresponding bit in PFDR, and the register value is read from PFDR regardless of the state of the
pin.
If a pin is set to the general input function, the pin state, not the register value, will be returned if
PFDR is read. Also, if a value is written to PFDR, although the value will actually be written, it
will have no influence on the state of the pin. Table 22.11 summarizes the PFDR read/write
operations.
PFDR is initialized to H'0000 by a power-on reset or in deep standby mode. This register is not
initialized either by a manual reset or by switching to sleep mode or software standby mode.
Table 22.11 Port F Data Register (PFDR) Read/Write Operations
R01UH0026EJ0300 Rev. 3.00
Sep 24, 2010
PFIOR
0
1
Initial value:
R/W:
Bit:
Port F Data Register (PFDR)
15
—
R
0
Pin Function
General input
Other than general
input
General output
Other than general
output
14
—
R
0
13
—
R
0
12
—
R
0
11
—
R
0
Read
Pin state
Pin state
Value of PFDR
Value of PFDR
10
—
R
0
—
R
9
0
—
R
8
0
R/W
PF7
DR
Write
The value is written to PFDR but there is
no effect on the pin state.
The value is written to PFDR but there is
no effect on the pin state.
The value written is output from the pin.
The value is written to PFDR but there is
no effect on the pin state.
7
0
R/W
PF6
DR
6
0
R/W
PF5
DR
5
0
R/W
PF4
DR
4
0
R/W
PF3
DR
3
0
R/W
Section 22 I/O Ports
PF2
DR
2
0
Page 925 of 1190
R/W
PF1
DR
1
0
R/W
PF0
DR
0
0