DS72011RB120FPV Renesas Electronics America, DS72011RB120FPV Datasheet - Page 195

• Manufacturer Part Number: DS72011RB120FPV
• Description: IC SH7201 MPU ROMLESS 176LQFP
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7200r

Specifications of DS72011RB120FPV

• Core Size: 32-Bit
• Core Processor: SH-2A
• Speed: 120MHz
• Connectivity: CAN, EBI/EMI, FIFO, I²C, SCI, Serial Sound
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 104
• Program Memory Type: ROMless
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 70°C
• Package / Case: 176-LQFP
• No. Of I/o's: 109
• Ram Memory Size: 32KB
• Cpu Speed: 120MHz
• Digital Ic Case Style: LQFP
• Supply Voltage Range: 3V To 3.6V
• Operating Temperature Range: -20°C To +70°C
• Embedded Interface Type: I2C, SSI
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: R0K572011S000BE - KIT STARTER FOR SH7201HS0005KCU11H - EMULATOR E10A-USB H8S(X),SH2(A)
• Eeprom Size: -
• Program Memory Size: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant

SH7201 Group
7.3.4
BDMR is a 32-bit readable/writable register. BDMR specifies bits masked in the break data bits
specified by BDR. BDMR is initialized to H'00000000 by a power-on reset or in deep standby, but
retains its previous value by a manual reset or in software standby mode or sleep mode.
Notes: 1. Set the operand size when specifying a value on a data bus as the break condition.
R01UH0026EJ0300 Rev. 3.00
Sep 24, 2010
Bit
31 to 0
Initial value:
Initial value:
R/W:
R/W:
Bit:
Bit:
2. When the byte size is selected as a break condition, the same byte data must be set in
Break Data Mask Register (BDMR)
BDM31 BDM30 BDM29 BDM28 BDM27 BDM26 BDM25 BDM24 BDM23 BDM22 BDM21 BDM20 BDM19 BDM18 BDM17 BDM16
BDM15 BDM14 BDM13 BDM12 BDM11 BDM10 BDM9 BDM8 BDM7 BDM6 BDM5 BDM4 BDM3 BDM2 BDM1 BDM0
Bit Name
BDM31 to
BDM0
R/W
R/W
bits 31 to 24, 23 to 16, 15 to 8, and 7 to 0 in BDMR as the break mask data. Similarly,
when the word size is selected, the same word data must be set in bits 31 to 16 and 15
to 0.
31
15
0
0
R/W
R/W
30
14
0
0
R/W
R/W
29
13
0
0
Initial
Value
All 0
R/W
R/W
28
12
0
0
R/W
R/W
27
11
0
0
R/W
R/W
R/W
R/W
26
10
0
0
Description
Specify bits masked in the break data bits specified by
BDR (BD31 to BD0).
0: Break data bit BDn is included in the break condition
1: Break data bit BDn is masked and not included in
Note: n = 31 to 0
Break Data Mask
R/W
R/W
25
0
9
0
the break condition
R/W
R/W
24
0
8
0
R/W
R/W
23
0
7
0
R/W
R/W
22
0
6
0
R/W
R/W
21
0
5
0
Section 7 User Break Controller (UBC)
R/W
R/W
20
0
4
0
R/W
R/W
19
0
3
0
R/W
R/W
18
0
2
0
Page 167 of 1190
R/W
R/W
17
0
1
0
R/W
R/W
16
0
0
0