DS72011RB120FPV Renesas Electronics America, DS72011RB120FPV Datasheet - Page 17

• Manufacturer Part Number: DS72011RB120FPV
• Description: IC SH7201 MPU ROMLESS 176LQFP
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7200r

Specifications of DS72011RB120FPV

• Core Size: 32-Bit
• Core Processor: SH-2A
• Speed: 120MHz
• Connectivity: CAN, EBI/EMI, FIFO, I²C, SCI, Serial Sound
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 104
• Program Memory Type: ROMless
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 70°C
• Package / Case: 176-LQFP
• No. Of I/o's: 109
• Ram Memory Size: 32KB
• Cpu Speed: 120MHz
• Digital Ic Case Style: LQFP
• Supply Voltage Range: 3V To 3.6V
• Operating Temperature Range: -20°C To +70°C
• Embedded Interface Type: I2C, SSI
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: R0K572011S000BE - KIT STARTER FOR SH7201HS0005KCU11H - EMULATOR E10A-USB H8S(X),SH2(A)
• Eeprom Size: -
• Program Memory Size: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant

12.4
12.5
12.6
12.7
R01UH0026EJ0300 Rev. 3.00
Sep 24, 2010
12.3.28 Timer Interrupt Skipping Counter (TITCNT)................................................... 448
12.3.29 Timer Buffer Transfer Set Register (TBTER) .................................................. 449
12.3.30 Timer Dead Time Enable Register (TDER)...................................................... 451
12.3.31 Timer Waveform Control Register (TWCR) .................................................... 452
12.3.32 Bus Master Interface ......................................................................................... 453
Operation .......................................................................................................................... 454
12.4.1
12.4.2
12.4.3
12.4.4
12.4.5
12.4.6
12.4.7
12.4.8
12.4.9
12.4.10 External Pulse Width Measurement.................................................................. 528
12.4.11 Dead Time Compensation................................................................................. 529
12.4.12 TCNT Capture at Crest and/or Trough in Complementary PWM Operation ... 531
Interrupt Sources............................................................................................................... 532
12.5.1
12.5.2
12.5.3
Operation Timing.............................................................................................................. 536
12.6.1
12.6.2
Usage Notes ...................................................................................................................... 548
12.7.1
12.7.2
12.7.3
12.7.4
12.7.5
12.7.6
12.7.7
12.7.8
12.7.9
12.7.10 Contention between TGR Write and Input Capture.......................................... 555
12.7.11 Contention between Buffer Register Write and Input Capture ......................... 556
12.7.12 TCNT_2 Write and Overflow/Underflow Contention
12.7.13 Counter Value during Complementary PWM Mode Stop ................................ 558
Basic Functions................................................................................................. 454
Synchronous Operation..................................................................................... 460
Buffer Operation ............................................................................................... 462
Cascaded Operation .......................................................................................... 467
PWM Modes ..................................................................................................... 472
Phase Counting Mode ....................................................................................... 477
Reset-Synchronized PWM Mode...................................................................... 484
Complementary PWM Mode ............................................................................ 487
A/D Converter Start Request Delaying Function.............................................. 524
Interrupt Sources and Priorities......................................................................... 532
DMAC Activation............................................................................................. 534
A/D Converter Activation................................................................................. 534
Input/Output Timing ......................................................................................... 536
Interrupt Signal Timing..................................................................................... 543
Module Standby Mode Setting ......................................................................... 548
Input Clock Restrictions ................................................................................... 548
Caution on Period Setting ................................................................................. 549
Contention between TCNT Write and Clear Operations.................................. 549
Contention between TCNT Write and Increment Operations........................... 550
Contention between TGR Write and Compare Match ...................................... 551
Contention between Buffer Register Write and Compare Match ..................... 552
Contention between Buffer Register Write and TCNT Clear ........................... 553
Contention between TGR Read and Input Capture........................................... 554
in Cascade Connection...................................................................................... 556
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