DS72011RB120FPV Renesas Electronics America, DS72011RB120FPV Datasheet - Page 244
![IC SH7201 MPU ROMLESS 176LQFP](/photos/28/61/286154/176-lqfp_sml.jpg)
DS72011RB120FPV
Manufacturer Part Number
DS72011RB120FPV
Description
IC SH7201 MPU ROMLESS 176LQFP
Manufacturer
Renesas Electronics America
Series
SuperH® SH7200r
Datasheet
1.R0K572011S000BE.pdf
(1222 pages)
Specifications of DS72011RB120FPV
Core Size
32-Bit
Core Processor
SH-2A
Speed
120MHz
Connectivity
CAN, EBI/EMI, FIFO, I²C, SCI, Serial Sound
Peripherals
DMA, POR, PWM, WDT
Number Of I /o
104
Program Memory Type
ROMless
Ram Size
32K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Data Converters
A/D 8x10b; D/A 2x8b
Oscillator Type
Internal
Operating Temperature
-20°C ~ 70°C
Package / Case
176-LQFP
No. Of I/o's
109
Ram Memory Size
32KB
Cpu Speed
120MHz
Digital Ic Case Style
LQFP
Supply Voltage Range
3V To 3.6V
Operating Temperature Range
-20°C To +70°C
Embedded Interface Type
I2C, SSI
Rohs Compliant
Yes
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
R0K572011S000BE - KIT STARTER FOR SH7201HS0005KCU11H - EMULATOR E10A-USB H8S(X),SH2(A)
Eeprom Size
-
Program Memory Size
-
Lead Free Status / RoHS Status
Lead free / RoHS Compliant, Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
DS72011RB120FPV
Manufacturer:
Renesas Electronics America
Quantity:
10 000
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Section 9 Bus State Controller (BSC)
Notes: 1. Make sure the page read and page write cycle wait select (CSPRWAIT and
Page 216 of 1190
Bit
10 to 8
7 to 3
2 to 0
2. Writing to the CSn wait control register 1 (CS1WCNTn) must be done while CSC for the
CSPRWAIT
Bit Name
[2:0]
⎯
CSPWWAIT
[2:0]
CSPWWAIT) settings are within the range defined by the read and write cycle wait
select (CSRWAIT and CSWWAIT) settings. Select each wait cycle number according
the system configuration incorporated.
corresponding channel is disabled (EXENB = 0). Only channel 0 (CS0) can be enabled
by setting EXENB = 1. To enable channel 0, stop the DMAC and set EXENB to 1
between the reset release and data write access to CS0.
Initial
Value
111
All 0
111
R/W
R/W
R
R/W
Description
Page Read Cycle Wait Select
These bits specify the number of wait states inserted
into the second and subsequent page read cycles. This
setting is valid when the page read access enable bit
(PRENB) is set to 1.
000: 0 wait state
111: 7 wait states
Reserved
These bits are always read as 0. The write value
should always be 0.
Page Write Cycle Wait Select
These bits specify the number of wait states inserted
into the second and subsequent page write cycles.
This setting is valid when the page write access enable
bit (PWENB) is set to 1.
000: 0 wait state
111: 7 wait states
:
:
R01UH0026EJ0300 Rev. 3.00
SH7201 Group
Sep 24, 2010
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