DS72011RB120FPV Renesas Electronics America, DS72011RB120FPV Datasheet - Page 662

• Manufacturer Part Number: DS72011RB120FPV
• Description: IC SH7201 MPU ROMLESS 176LQFP
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7200r

Specifications of DS72011RB120FPV

• Core Size: 32-Bit
• Core Processor: SH-2A
• Speed: 120MHz
• Connectivity: CAN, EBI/EMI, FIFO, I²C, SCI, Serial Sound
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 104
• Program Memory Type: ROMless
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 70°C
• Package / Case: 176-LQFP
• No. Of I/o's: 109
• Ram Memory Size: 32KB
• Cpu Speed: 120MHz
• Digital Ic Case Style: LQFP
• Supply Voltage Range: 3V To 3.6V
• Operating Temperature Range: -20°C To +70°C
• Embedded Interface Type: I2C, SSI
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: R0K572011S000BE - KIT STARTER FOR SH7201HS0005KCU11H - EMULATOR E10A-USB H8S(X),SH2(A)
• Eeprom Size: -
• Program Memory Size: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant

Section 14 Watchdog Timer (WDT)
14.4.3
1. Set the WT/IT bit in WTCSR to 1, the type of count clock in the CKS[2:0] bits in WTCSR,
2. Set the TME bit in WTCSR to 1 to start the count in watchdog timer mode.
3. While operating in watchdog timer mode, rewrite the counter periodically to H'00 to prevent
4. When the counter overflows, the WDT sets the WOVF flag in WRCSR to 1, and the
5. If the RSTE bit in WRCSR is set to 1, a signal to reset the inside of this LSI can be generated
6. When a WDT overflow reset is generated simultaneously with a reset input on the RES pin,
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Internal
reset signal*
[Legend]
WT/IT:
TME:
Note: * Internal reset signal occurs only when the RSTE bit is set to 1.
WDTOVF
signal
whether this LSI is to be reset internally or not in the RSTE bit in WRCSR, the reset type if it
is generated in the RSTS bit in WRCSR, and the initial value of the counter in WTCNT.
the counter from overflowing.
WDTOVF signal is output externally (figure 14.4). The WDTOVF signal can be used to reset
the system. The WDTOVF signal is output for 64 × Pφ clock cycles.
simultaneously with the WDTOVF signal. Either power-on reset or manual reset can be
selected for this interrupt by the RSTS bit in WRCSR. The internal reset signal is output for
128 × Pφ clock cycles.
the RES pin reset takes priority, and the WOVF bit in WRCSR is cleared to 0.
WTCNT value
H'FF
H'00
Timer mode select bit
Timer enable bit
Using Watchdog Timer Mode
WT/IT = 1
TME = 1
Figure 14.4 Operation in Watchdog Timer Mode
H'00 written
in WTCNT
WDTOVF and internal reset generated
64
WOVF = 1
128
Overflow
P clock cycles
P clock cycles
WT/IT = 1
TME = 1
R01UH0026EJ0300 Rev. 3.00
H'00 written
in WTCNT
SH7201 Group
Sep 24, 2010
Time