DS72011RB120FPV Renesas Electronics America, DS72011RB120FPV Datasheet - Page 31
![IC SH7201 MPU ROMLESS 176LQFP](/photos/28/61/286154/176-lqfp_sml.jpg)
DS72011RB120FPV
Manufacturer Part Number
DS72011RB120FPV
Description
IC SH7201 MPU ROMLESS 176LQFP
Manufacturer
Renesas Electronics America
Series
SuperH® SH7200r
Datasheet
1.R0K572011S000BE.pdf
(1222 pages)
Specifications of DS72011RB120FPV
Core Size
32-Bit
Core Processor
SH-2A
Speed
120MHz
Connectivity
CAN, EBI/EMI, FIFO, I²C, SCI, Serial Sound
Peripherals
DMA, POR, PWM, WDT
Number Of I /o
104
Program Memory Type
ROMless
Ram Size
32K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Data Converters
A/D 8x10b; D/A 2x8b
Oscillator Type
Internal
Operating Temperature
-20°C ~ 70°C
Package / Case
176-LQFP
No. Of I/o's
109
Ram Memory Size
32KB
Cpu Speed
120MHz
Digital Ic Case Style
LQFP
Supply Voltage Range
3V To 3.6V
Operating Temperature Range
-20°C To +70°C
Embedded Interface Type
I2C, SSI
Rohs Compliant
Yes
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
R0K572011S000BE - KIT STARTER FOR SH7201HS0005KCU11H - EMULATOR E10A-USB H8S(X),SH2(A)
Eeprom Size
-
Program Memory Size
-
Lead Free Status / RoHS Status
Lead free / RoHS Compliant, Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
DS72011RB120FPV
Manufacturer:
Renesas Electronics America
Quantity:
10 000
- Current page: 31 of 1222
- Download datasheet (8Mb)
SH7201 Group
R01UH0026EJ0300 Rev. 3.00
Sep 24, 2010
Item
Floating-point Unit
(FPU)
Cache
Interrupt controller
(INTC)
Features
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Floating-point co-processor included
Supports single-precision (32-bit) and double-precision (64-bit)
Supports data type and exceptions that conforms to IEEE754 standard
Two rounding modes: Round to nearest and round to zero
Denormalization modes: Flush to zero
Floating-point registers
Sixteen 32-bit floating-point registers (single-precision × 16 words or
double-precision × 8 words)
Two 32-bit floating-point system registers
Supports FMAC (multiplication and accumulation) instructions
Supports FDIV (division) and FSQRT (square root) instructions
Supports FLDI0/FLDI1 (load constant 0/1) instructions
Instruction execution time
Latency (FAMC/FADD/FSUB/FMUL): Three cycles (single-precision),
eight cycles (double-precision)
Pitch (FAMC/FADD/FSUB/FMUL): One cycle (single-precision), six
cycles (double-precision)
Note: FMAC only supports single-precision
5-stage pipeline
Instruction cache: 8 Kbytes
Operand cache: 8 Kbytes
128-entry, 4-way set associative, 16-byte block length configuration
each for the instruction cache and operand cache
Write-back, write-through and LRU replacement algorithm
Cache locking function available (only for operand cache); ways 2 and
3 can be locked
Seventeen external interrupt pins (NMI, IRQ7 to IRQ0, and PINT7 to
PINT0)
On-chip peripheral interrupts: Priority level set for each module
16 priority levels available
Register bank enabling fast register saving and restoring in interrupt
handling
Section 1 Overview
Page 3 of 1190
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