DS72011RB120FPV Renesas Electronics America, DS72011RB120FPV Datasheet - Page 348

• Manufacturer Part Number: DS72011RB120FPV
• Description: IC SH7201 MPU ROMLESS 176LQFP
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7200r

Specifications of DS72011RB120FPV

• Core Size: 32-Bit
• Core Processor: SH-2A
• Speed: 120MHz
• Connectivity: CAN, EBI/EMI, FIFO, I²C, SCI, Serial Sound
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 104
• Program Memory Type: ROMless
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 70°C
• Package / Case: 176-LQFP
• No. Of I/o's: 109
• Ram Memory Size: 32KB
• Cpu Speed: 120MHz
• Digital Ic Case Style: LQFP
• Supply Voltage Range: 3V To 3.6V
• Operating Temperature Range: -20°C To +70°C
• Embedded Interface Type: I2C, SSI
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: R0K572011S000BE - KIT STARTER FOR SH7201HS0005KCU11H - EMULATOR E10A-USB H8S(X),SH2(A)
• Eeprom Size: -
• Program Memory Size: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant

Section 11 Direct Memory Access Controller (DMAC)
Page 320 of 1190
Bit
17, 16
15 to 11 ⎯
10
Bit Name
STRG[1:0]
BRLOD
Initial
Value
All 0
00
0
R/W
R/W
R
R/W
Description
Input Sense Mode Selection
These bits specify input sense modes for DMA request
signals input to the DMAC. The requesting source is
that selected from among the possible sources by the
DMA request source selection bits (DCTG).
Select rising edge sense by setting these bits to "00" if
the software trigger (DCTG = "000000") and pins
DREQ0 to DREQ3 are selected as the source for DMA
requests. Select falling edge sense by setting the bits
to "10" when operation is with IIC3, SCIF, SSI, RCAN-
ET, MTU2, or ADC (DCTG = "000101" to "100100").
Table 11.4 shows the relationships between DMA
request sources and the possible input sense modes.
00: Rising edge
01: High level
10: Falling edge
11: Low level
Reserved
These bits are always read as 0. The write value
should always be 0.
DMA Byte Count Reload Function Enable
This bit specifies whether to reload the byte counter or
not when the DMA transfer end condition is detected.
When this bit is cleared to "0", no reload is executed.
When this bit is set to "1" and the DMA transfer end
condition is detected, the DMA current byte counter
register (DMCBCTn) is reloaded with the value in the
DMA reload byte count register (DMRBCTn).
0: Byte count reload function disabled
1: Byte count reload function enabled
R01UH0026EJ0300 Rev. 3.00
SH7201 Group
Sep 24, 2010