DS72011RB120FPV Renesas Electronics America, DS72011RB120FPV Datasheet - Page 459

• Manufacturer Part Number: DS72011RB120FPV
• Description: IC SH7201 MPU ROMLESS 176LQFP
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7200r

Specifications of DS72011RB120FPV

• Core Size: 32-Bit
• Core Processor: SH-2A
• Speed: 120MHz
• Connectivity: CAN, EBI/EMI, FIFO, I²C, SCI, Serial Sound
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 104
• Program Memory Type: ROMless
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 70°C
• Package / Case: 176-LQFP
• No. Of I/o's: 109
• Ram Memory Size: 32KB
• Cpu Speed: 120MHz
• Digital Ic Case Style: LQFP
• Supply Voltage Range: 3V To 3.6V
• Operating Temperature Range: -20°C To +70°C
• Embedded Interface Type: I2C, SSI
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: R0K572011S000BE - KIT STARTER FOR SH7201HS0005KCU11H - EMULATOR E10A-USB H8S(X),SH2(A)
• Eeprom Size: -
• Program Memory Size: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant

SH7201 Group
12.3.16 Timer Counter Synchronous Start Register (TCSYSTR)
TCSYSTR is an 8-bit readable/writable register that specifies synchronous start of the MTU2
counters.
R01UH0026EJ0300 Rev. 3.00
Sep 24, 2010
Bit
7
6
5
Bit Name
SCH0
SCH1
SCH2
Initial value:
Initial
Value
0
0
0
Note:
R/W:
*
Bit:
Only 1 can be written to set the register.
R/(W)*R/(W)*R/(W)*R/(W)*R/(W)*
SCH0 SCH1 SCH2 SCH3 SCH4
R/W
R/(W)* Synchronous Start
R/(W)* Synchronous Start
R/(W)* Synchronous Start
7
0
6
0
Description
Controls synchronous start of TCNT_0 in the MTU2.
0: Does not specify synchronous start for TCNT_0 in
1: Specifies synchronous start for TCNT_0 in the MTU2
[Clearing condition]
•
Controls synchronous start of TCNT_1 in the MTU2.
0: Does not specify synchronous start for TCNT_1 in
1: Specifies synchronous start for TCNT_1 in the MTU2
[Clearing condition]
•
Controls synchronous start of TCNT_2 in the MTU2.
0: Does not specify synchronous start for TCNT_2 in
1: Specifies synchronous start for TCNT_2 in the MTU2
[Clearing condition]
•
5
0
the MTU2
the MTU2
the MTU2
When 1 is set to the CST0 bit of TSTR in MTU2
while SCH0 = 1
When 1 is set to the CST1 bit of TSTR in MTU2
while SCH1 = 1
When 1 is set to the CST2 bit of TSTR in MTU2
while SCH2 = 1
4
0
3
0
Section 12 Multi-Function Timer Pulse Unit 2 (MTU2)
—
R
2
0
—
R
1
0
—
R
0
0
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