DS72011RB120FPV Renesas Electronics America, DS72011RB120FPV Datasheet - Page 219

• Manufacturer Part Number: DS72011RB120FPV
• Description: IC SH7201 MPU ROMLESS 176LQFP
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7200r

Specifications of DS72011RB120FPV

• Core Size: 32-Bit
• Core Processor: SH-2A
• Speed: 120MHz
• Connectivity: CAN, EBI/EMI, FIFO, I²C, SCI, Serial Sound
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 104
• Program Memory Type: ROMless
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 70°C
• Package / Case: 176-LQFP
• No. Of I/o's: 109
• Ram Memory Size: 32KB
• Cpu Speed: 120MHz
• Digital Ic Case Style: LQFP
• Supply Voltage Range: 3V To 3.6V
• Operating Temperature Range: -20°C To +70°C
• Embedded Interface Type: I2C, SSI
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: R0K572011S000BE - KIT STARTER FOR SH7201HS0005KCU11H - EMULATOR E10A-USB H8S(X),SH2(A)
• Eeprom Size: -
• Program Memory Size: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant

SH7201 Group
8.3.2
(1)
In a read access, data is transferred from the cache to the CPU. LRU is updated so that the hit way
is the latest.
(2)
An external bus cycle starts and the entry is updated. The way replaced follows table 8.4. Entries
are updated in 16-byte units. When the desired data that caused the miss is loaded from external
memory to the cache, the data is transferred to the CPU in parallel with being loaded to the cache.
When it is loaded in the cache, the V bit is set to 1, and LRU is updated so that the replaced way
becomes the latest. In operand cache, the U bit is additionally cleared to 0. When the U bit of the
entry to be replaced by updating the entry in write-back mode is 1, the cache update cycle starts
after the entry is transferred to the write-back buffer. After the cache completes its update cycle,
the write-back buffer writes the entry back to the memory. The write-back unit is 16 bytes.
8.3.3
(1)
LRU is updated so that the hit way becomes the latest. The contents in other caches are not
modified. No data is transferred to the CPU.
(2)
No data is transferred to the CPU. The way to be replaced follows table 8.3. Other operations are
the same in case of read miss.
8.3.4
(1)
In a write access in write-back mode, the data is written to the cache and no external memory
write cycle is issued. The U bit of the entry written is set to 1 and LRU is updated so that the hit
way becomes the latest.
In write-through mode, the data is written to the cache and an external memory write cycle is
issued. The U bit of the written entry is not updated and LRU is updated so that the replaced way
becomes the latest.
R01UH0026EJ0300 Rev. 3.00
Sep 24, 2010
Read Hit
Read Miss
Prefetch Hit
Prefetch Miss
Write Hit
Read Access
Prefetch Operation (Only for Operand Cache)
Write Operation (Only for Operand Cache)
Section 8 Cache
Page 191 of 1190