DS72011RB120FPV Renesas Electronics America, DS72011RB120FPV Datasheet - Page 85
![IC SH7201 MPU ROMLESS 176LQFP](/photos/28/61/286154/176-lqfp_sml.jpg)
DS72011RB120FPV
Manufacturer Part Number
DS72011RB120FPV
Description
IC SH7201 MPU ROMLESS 176LQFP
Manufacturer
Renesas Electronics America
Series
SuperH® SH7200r
Datasheet
1.R0K572011S000BE.pdf
(1222 pages)
Specifications of DS72011RB120FPV
Core Size
32-Bit
Core Processor
SH-2A
Speed
120MHz
Connectivity
CAN, EBI/EMI, FIFO, I²C, SCI, Serial Sound
Peripherals
DMA, POR, PWM, WDT
Number Of I /o
104
Program Memory Type
ROMless
Ram Size
32K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Data Converters
A/D 8x10b; D/A 2x8b
Oscillator Type
Internal
Operating Temperature
-20°C ~ 70°C
Package / Case
176-LQFP
No. Of I/o's
109
Ram Memory Size
32KB
Cpu Speed
120MHz
Digital Ic Case Style
LQFP
Supply Voltage Range
3V To 3.6V
Operating Temperature Range
-20°C To +70°C
Embedded Interface Type
I2C, SSI
Rohs Compliant
Yes
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
R0K572011S000BE - KIT STARTER FOR SH7201HS0005KCU11H - EMULATOR E10A-USB H8S(X),SH2(A)
Eeprom Size
-
Program Memory Size
-
Lead Free Status / RoHS Status
Lead free / RoHS Compliant, Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
DS72011RB120FPV
Manufacturer:
Renesas Electronics America
Quantity:
10 000
- Current page: 85 of 1222
- Download datasheet (8Mb)
SH7201 Group
R01UH0026EJ0300 Rev. 3.00
Sep 24, 2010
Instruction
FMOV.S
FMOV.D
FMOV.S
FMOV.D
FMOV.S
FMOV.D
FMOV.S
FMOV.D
FMOV.S
FMOV.D
FMOV.S
FMOV.D
FMUL
FMUL
FNEG
FNEG
FSCHG
FSQRT
FSQRT
FSTS
FSUB
FSUB
FTRC
FTRC
@(disp12,Rm),FRn
@(disp12,Rm),DRn
FRm, @(R0,Rn)
DRm, @( R0,Rn )
FRm, @-Rn
DRm, @-Rn
FRm, @Rn
DRm, @Rn
FRm, @(disp12,Rn) 0011nnnnmmmm000100
DRm, @(disp12,Rn) 0011nnnnmmm0000100
FRm, FRn
DRm, DRn
FRn
DRn
FRn
DRn
FPUL,FRn
FRm, FRn
DRm, DRn
FRm, FPUL
DRm, FPUL
@Rm, FRn
@Rm, DRn
Instruction Code
1111nnnnmmmm1000
1111nnn0mmmm1000
0011nnnnmmmm0001
0111dddddddddddd
0011nnn0mmmm0001
0111dddddddddddd
1111nnnnmmmm0111
1111nnnnmmm00111
1111nnnnmmmm1011
1111nnnnmmm01011
1111nnnnmmmm1010
1111nnnnmmm01010
11dddddddddddd
11dddddddddddd
1111nnnnmmmm0010
1111nnn0mmm00010
1111nnnn01001101
1111nnn001001101
1111001111111101
1111nnnn01101101
1111nnn001101101
1111nnnn00001101
1111nnnnmmmm0001
1111nnn0mmm00001
1111mmmm00111101
1111mmm000111101
Operation
(Rm) →FRn
(Rm) →DRn
(disp×4+Rm) →FRn
(disp×8+Rm) →DRn
FRm→ (R0+Rn)
DRm→ (R0+Rn)
Rn-=4, FRm→(Rn)
Rn-=8, DRm→(Rn)
FRm→(Rn)
DRm→(Rn)
FRm→(disp×4+Rn)
DRm→(disp×8+Rn)
FRn×FRm→FRn
DRn×DRm→DRn
-FRn→FRn
-DRn→DRn
FPSCR.SZ=~FPSCR.SZ
√FRn→FRn
√DRn→DRn
FPUL→FRn
FRn-FRm→FRn
DRn-DRm→DRn
(long)FRm→FPUL
(long)DRm→FPUL
Execution
Cycles
1
2
1
2
1
2
1
2
1
2
1
2
1
6
1
1
1
9
22
1
1
6
1
2
T Bit
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
SH2E
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Compatibility
SH4
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Page 57 of 1190
Section 2 CPU
SH-2A/
SH2A-FPU
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
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