DS72011RB120FPV Renesas Electronics America, DS72011RB120FPV Datasheet - Page 837

• Manufacturer Part Number: DS72011RB120FPV
• Description: IC SH7201 MPU ROMLESS 176LQFP
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7200r

Specifications of DS72011RB120FPV

• Core Size: 32-Bit
• Core Processor: SH-2A
• Speed: 120MHz
• Connectivity: CAN, EBI/EMI, FIFO, I²C, SCI, Serial Sound
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 104
• Program Memory Type: ROMless
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 70°C
• Package / Case: 176-LQFP
• No. Of I/o's: 109
• Ram Memory Size: 32KB
• Cpu Speed: 120MHz
• Digital Ic Case Style: LQFP
• Supply Voltage Range: 3V To 3.6V
• Operating Temperature Range: -20°C To +70°C
• Embedded Interface Type: I2C, SSI
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: R0K572011S000BE - KIT STARTER FOR SH7201HS0005KCU11H - EMULATOR E10A-USB H8S(X),SH2(A)
• Eeprom Size: -
• Program Memory Size: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant

SH7201 Group
18.5
18.5.1
If an overflow occurs while the receive DMA is in operation, the module should be restarted. The
receive buffer in the SSI consists of 32-bit registers that share the L and R channels. Therefore,
data to be received at the L channel may sometimes be received at the R channel if an overflow
occurs, for example, under the following condition: the control register (SSICR) has a 32-bit
setting for both data word length (DWL2 to DWL0) and system word length (SWL2 to SWL0).
If an overflow is confirmed with the overflow error interrupt or overflow error status flag (the
OIRQ bit in SSISR), write 0 to the EN bit in SSICR and DMEN bit to disable DMA in the SSI
module, thus stopping the operation. (In this case, the controller setting should also be stopped.)
After this, write 0 to the OIRQ bit to clear the overflow status, set DMA again and restart the
transfer.
18.5.2
To use the externally input clock as the oversample clock, refer to the section 4.6.1, Note on
Inputting External Clock, in which the terms EXTAL and XTAL pins should be replaced by the
AUDIO_X1 and AUDIO_X2 pins respectively.
To use the crystal resonator, refer to the section 4.6.2, Note on Using Crystal Resonator, in which
the terms EXTAL and XTAL pins should be replaced by the AUDIO_X1 and AUDIO_X2 pins
respectively.
Also, see section 4.6.3, Note on Resonator.
18.5.3
Once the bits MSTP53 and MSTP52 in the standby control register 5 (STBCR5) are cleared to 0
and the SSI operation is started, do not set these bits to 1 (stops clock supply to the SSI).
R01UH0026EJ0300 Rev. 3.00
Sep 24, 2010
Usage Notes
Limitations from Overflow during Receive DMA Operation
Note on Using Oversample Clock
Restriction on Stopping Clock Supply
Section 18 Serial Sound Interface (SSI)
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