DS72011RB120FPV Renesas Electronics America, DS72011RB120FPV Datasheet - Page 278

• Manufacturer Part Number: DS72011RB120FPV
• Description: IC SH7201 MPU ROMLESS 176LQFP
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7200r

Specifications of DS72011RB120FPV

• Core Size: 32-Bit
• Core Processor: SH-2A
• Speed: 120MHz
• Connectivity: CAN, EBI/EMI, FIFO, I²C, SCI, Serial Sound
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 104
• Program Memory Type: ROMless
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 70°C
• Package / Case: 176-LQFP
• No. Of I/o's: 109
• Ram Memory Size: 32KB
• Cpu Speed: 120MHz
• Digital Ic Case Style: LQFP
• Supply Voltage Range: 3V To 3.6V
• Operating Temperature Range: -20°C To +70°C
• Embedded Interface Type: I2C, SSI
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: R0K572011S000BE - KIT STARTER FOR SH7201HS0005KCU11H - EMULATOR E10A-USB H8S(X),SH2(A)
• Eeprom Size: -
• Program Memory Size: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant

Section 9 Bus State Controller (BSC)
(5)
An auto-refresh cycle starts when the auto-refresh operation enable bit (DRFEN) in SDRAM
refresh control register 1 (SDRFCNT1) is set to 1. After that refresh requests are issued at fixed
intervals, activating auto-refresh cycles. However, the activation of auto-refresh cycles may
sometimes be delayed because refresh requests are not accepted during read or write accesses.
A refresh request is issued immediately if the auto-refresh operation enable bit (DRFEN) in
SDRAM refresh control register 1 (SDRFCNT1) is set to 1 while auto-refresh is enabled.
The refresh counter is halted in self-refresh or deep-power-down mode. After recovery from self-
refresh or deep-power-down mode an auto-refresh cycle is activated, after which the counter value
is reset and the counter begins operating again
Make auto-refresh settings in SDRAM refresh control register 1 (SDRFCNT1). Note that refresh
cycles affect all SDRAM channels. Figure 9.9 shows an auto-refresh cycle timing example.
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Auto-Refresh
CKIO
SDRAM command
Figure 9.9 Auto-Refresh Cycle Timing Example (DREFW Bit Set Value: 0010)
Figure 9.8 Example of Timing of Recovery from Self-Refresh Mode
DSL: Deselect command
RFA: Auto-refresh command
RFX: Self-refresh exit command
Self-refresh mode
CKIO
SDRAM command
(CKE = L)
(DREFW Bit Set Value: 0010)
DSL: Deselect command
RFA: Auto-refresh command
Self-refresh clearing
REX
Auto-refresh cycle
RFA
interval
DREFW
DSL
DREFW
DSL
DSL
DSL
RFA
Auto-refresh
cycle
DREFW
DSL
R01UH0026EJ0300 Rev. 3.00
DSL
SH7201 Group
Sep 24, 2010