DS72011RB120FPV Renesas Electronics America, DS72011RB120FPV Datasheet - Page 318

• Manufacturer Part Number: DS72011RB120FPV
• Description: IC SH7201 MPU ROMLESS 176LQFP
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7200r

Specifications of DS72011RB120FPV

• Core Size: 32-Bit
• Core Processor: SH-2A
• Speed: 120MHz
• Connectivity: CAN, EBI/EMI, FIFO, I²C, SCI, Serial Sound
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 104
• Program Memory Type: ROMless
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 70°C
• Package / Case: 176-LQFP
• No. Of I/o's: 109
• Ram Memory Size: 32KB
• Cpu Speed: 120MHz
• Digital Ic Case Style: LQFP
• Supply Voltage Range: 3V To 3.6V
• Operating Temperature Range: -20°C To +70°C
• Embedded Interface Type: I2C, SSI
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: R0K572011S000BE - KIT STARTER FOR SH7201HS0005KCU11H - EMULATOR E10A-USB H8S(X),SH2(A)
• Eeprom Size: -
• Program Memory Size: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant

Section 10 Bus Monitor
Page 290 of 1190
Bit
25, 24
23 to 14 ⎯
13
12 to 10 ⎯
9, 8
7, 6
5
Bit Name
EMST[1:0]
OER
OMST[1:0]
⎯
SHER
Initial
Value
00
All 0
0
All 0
00
All 0
0
R/W
R
R
R
R
R/W
R
R
Description
Bus Master
These bits indicate the bus master that accessed the
external bus when the first bus error occurred.
00: CPU
01: DMAC (destination side)
10: Setting prohibited
11: DMAC (source side)
Reserved
These bits are always read as 0. The write value
should always be 0.
Illegal Address Access
These bits indicate the bus master that accessed other
buses when the first bus error occurred.
0: Illegal address access not made
1: Illegal address access made
Reserved
These bits are always read as 0. The write value
should always be 0.
Bus Master
These bits indicate the bus master that accessed other
buses when the first bus error occurred.
00: CPU
01: DMAC (destination side)
10: Setting prohibited
11: DMAC (source side)
Reserved
These bits are always read as 0. The write value
should always be 0.
Illegal Address Access
This bit indicates that an illegal address access was
made on peripheral bus (2) when the first bus error
occurred.
0: Illegal address access not made
1: Illegal address access made
R01UH0026EJ0300 Rev. 3.00
SH7201 Group
Sep 24, 2010