DS72011RB120FPV Renesas Electronics America, DS72011RB120FPV Datasheet - Page 368
![IC SH7201 MPU ROMLESS 176LQFP](/photos/28/61/286154/176-lqfp_sml.jpg)
DS72011RB120FPV
Manufacturer Part Number
DS72011RB120FPV
Description
IC SH7201 MPU ROMLESS 176LQFP
Manufacturer
Renesas Electronics America
Series
SuperH® SH7200r
Datasheet
1.R0K572011S000BE.pdf
(1222 pages)
Specifications of DS72011RB120FPV
Core Size
32-Bit
Core Processor
SH-2A
Speed
120MHz
Connectivity
CAN, EBI/EMI, FIFO, I²C, SCI, Serial Sound
Peripherals
DMA, POR, PWM, WDT
Number Of I /o
104
Program Memory Type
ROMless
Ram Size
32K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Data Converters
A/D 8x10b; D/A 2x8b
Oscillator Type
Internal
Operating Temperature
-20°C ~ 70°C
Package / Case
176-LQFP
No. Of I/o's
109
Ram Memory Size
32KB
Cpu Speed
120MHz
Digital Ic Case Style
LQFP
Supply Voltage Range
3V To 3.6V
Operating Temperature Range
-20°C To +70°C
Embedded Interface Type
I2C, SSI
Rohs Compliant
Yes
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
R0K572011S000BE - KIT STARTER FOR SH7201HS0005KCU11H - EMULATOR E10A-USB H8S(X),SH2(A)
Eeprom Size
-
Program Memory Size
-
Lead Free Status / RoHS Status
Lead free / RoHS Compliant, Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
DS72011RB120FPV
Manufacturer:
Renesas Electronics America
Quantity:
10 000
- Current page: 368 of 1222
- Download datasheet (8Mb)
Section 11 Direct Memory Access Controller (DMAC)
11.4
11.4.1
There are two DMA transfer modes ⎯ cycle-stealing mode and pipelined mode. These modes are
selectable through the setting of the DMA transfer mode select bits (MDSEL) in DMA Control
Register A (DMCNTAn).
Figure 11.2 gives examples of how bus mastership alternates between the DMAC and CPU in
various DMA transfer modes.
(1)
Cycle-stealing transfer mode is selected when the DMA transfer mode select bits are set to "00".
In cycle-stealing transfer mode, the DMAC leaves at least one cycle between the read and write
access cycles of each single data transfer. During this interval, the CPU can access the same target
BIU as the source or destination of its own operations. For details on the BIU, see section 11.1,
Features.
(2)
Pipelined transfer mode is selected when the DMA transfer mode select bits are set to "01".
In pipelined transfer mode, DMAC activates the bus for read or write access, or both, on
consecutive cycles. Therefore, the CPU cannot access the target BIU as a source or destination
during single operand transfer.
Pipelined transfer through a single BIU is not possible either.
Page 340 of 1190
Cycle-stealing Transfer Mode
Pipelined Transfer Mode
Operation
DMA Transfer Mode
R01UH0026EJ0300 Rev. 3.00
SH7201 Group
Sep 24, 2010
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