DS72011RB120FPV Renesas Electronics America, DS72011RB120FPV Datasheet - Page 67
![IC SH7201 MPU ROMLESS 176LQFP](/photos/28/61/286154/176-lqfp_sml.jpg)
DS72011RB120FPV
Manufacturer Part Number
DS72011RB120FPV
Description
IC SH7201 MPU ROMLESS 176LQFP
Manufacturer
Renesas Electronics America
Series
SuperH® SH7200r
Datasheet
1.R0K572011S000BE.pdf
(1222 pages)
Specifications of DS72011RB120FPV
Core Size
32-Bit
Core Processor
SH-2A
Speed
120MHz
Connectivity
CAN, EBI/EMI, FIFO, I²C, SCI, Serial Sound
Peripherals
DMA, POR, PWM, WDT
Number Of I /o
104
Program Memory Type
ROMless
Ram Size
32K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Data Converters
A/D 8x10b; D/A 2x8b
Oscillator Type
Internal
Operating Temperature
-20°C ~ 70°C
Package / Case
176-LQFP
No. Of I/o's
109
Ram Memory Size
32KB
Cpu Speed
120MHz
Digital Ic Case Style
LQFP
Supply Voltage Range
3V To 3.6V
Operating Temperature Range
-20°C To +70°C
Embedded Interface Type
I2C, SSI
Rohs Compliant
Yes
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
R0K572011S000BE - KIT STARTER FOR SH7201HS0005KCU11H - EMULATOR E10A-USB H8S(X),SH2(A)
Eeprom Size
-
Program Memory Size
-
Lead Free Status / RoHS Status
Lead free / RoHS Compliant, Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
DS72011RB120FPV
Manufacturer:
Renesas Electronics America
Quantity:
10 000
- Current page: 67 of 1222
- Download datasheet (8Mb)
SH7201 Group
R01UH0026EJ0300 Rev. 3.00
Sep 24, 2010
Classification
Arithmetic
operations
Types
26
Operation
Code
ADD
ADDC
ADDV
CMP/cond Comparison
CLIPS
CLIPU
DIVS
DIVU
DIV1
DIV0S
DIV0U
DMULS
DMULU
DT
EXTS
EXTU
MAC
MUL
MULR
MULS
MULU
NEG
NEGC
SUB
SUBC
SUBV
Function
Binary addition
Binary addition with carry
Binary addition with overflow check
Signed saturation value comparison
Unsigned saturation value comparison
Signed division (32 ÷ 32)
Unsigned division (32 ÷ 32)
One-step division
Initialization of signed one-step division
Initialization of unsigned one-step division
Signed double-precision multiplication
Unsigned double-precision multiplication
Decrement and test
Sign extension
Zero extension
Multiply-and-accumulate, double-precision
multiply-and-accumulate operation
Double-precision multiply operation
Signed multiplication with result storage in Rn
Signed multiplication
Unsigned multiplication
Negation
Negation with borrow
Binary subtraction
Binary subtraction with borrow
Binary subtraction with underflow
No. of
Instructions
40
Page 39 of 1190
Section 2 CPU
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