DS72011RB120FPV Renesas Electronics America, DS72011RB120FPV Datasheet - Page 122

• Manufacturer Part Number: DS72011RB120FPV
• Description: IC SH7201 MPU ROMLESS 176LQFP
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7200r

Specifications of DS72011RB120FPV

• Core Size: 32-Bit
• Core Processor: SH-2A
• Speed: 120MHz
• Connectivity: CAN, EBI/EMI, FIFO, I²C, SCI, Serial Sound
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 104
• Program Memory Type: ROMless
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 70°C
• Package / Case: 176-LQFP
• No. Of I/o's: 109
• Ram Memory Size: 32KB
• Cpu Speed: 120MHz
• Digital Ic Case Style: LQFP
• Supply Voltage Range: 3V To 3.6V
• Operating Temperature Range: -20°C To +70°C
• Embedded Interface Type: I2C, SSI
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: R0K572011S000BE - KIT STARTER FOR SH7201HS0005KCU11H - EMULATOR E10A-USB H8S(X),SH2(A)
• Eeprom Size: -
• Program Memory Size: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant

Section 5 Exception Handling
When exception handling starts, the CPU operates as follows:
(1)
The initial values of the program counter (PC) and stack pointer (SP) are fetched from the
exception handling vector table (PC and SP are respectively the H'00000000 and H'00000004
addresses for power-on resets and the H'00000008 and H'0000000C addresses for manual resets).
See section 5.1.3, Exception Handling Vector Table, for more information. The vector base
register (VBR) is then initialized to H'00000000, the interrupt mask level bits (I3 to I0) of the
status register (SR) are initialized to H'F (B'1111), and the BO and CS bits are initialized. The BN
bit in IBNR of the interrupt controller (INTC) is also initialized to 0. FPSCR is initialized to
H'00040001 by a power-on reset. The program begins running from the PC address fetched from
the exception handling vector table.
(2)
SR and PC are saved to the stack indicated by R15. In the case of interrupt exception handling
other than the NMI or user break, with usage of the register banks enabled, general registers R0 to
R14, control register GBR, system registers MACH, MACL, and PR, and the vector number of the
interrupt exception handling to be executed are saved to the register banks. In the case of
exception handling due to an address error, bus error, register bank error, NMI interrupt, user
break interrupt, or instruction, saving to a register bank is not performed. When saving is
performed to all register banks, automatic saving to the stack is performed instead of register bank
saving. In this case, an interrupt controller setting must have been made so that register bank
overflow exceptions are not accepted (the BOVE bit in IBNR of the INTC is 0). If a setting to
accept register bank overflow exceptions has been made (the BOVE bit in IBNR of the INTC is
1), register bank overflow exception will be generated. In the case of interrupt exception handling,
the interrupt priority level is written to the I3 to I0 bits in SR. In the case of exception handling
due to an address error or instruction, the I3 to I0 bits are not affected. The start address is then
fetched from the exception handling vector table and the program begins running from that
address.
Page 94 of 1190
Exception Handling Triggered by Reset
Exception Handling Triggered by Address Errors, Bus Errors, Register Bank Errors,
Interrupts, and Instructions
R01UH0026EJ0300 Rev. 3.00
SH7201 Group
Sep 24, 2010