DS72011RB120FPV Renesas Electronics America, DS72011RB120FPV Datasheet - Page 272
![IC SH7201 MPU ROMLESS 176LQFP](/photos/28/61/286154/176-lqfp_sml.jpg)
DS72011RB120FPV
Manufacturer Part Number
DS72011RB120FPV
Description
IC SH7201 MPU ROMLESS 176LQFP
Manufacturer
Renesas Electronics America
Series
SuperH® SH7200r
Datasheet
1.R0K572011S000BE.pdf
(1222 pages)
Specifications of DS72011RB120FPV
Core Size
32-Bit
Core Processor
SH-2A
Speed
120MHz
Connectivity
CAN, EBI/EMI, FIFO, I²C, SCI, Serial Sound
Peripherals
DMA, POR, PWM, WDT
Number Of I /o
104
Program Memory Type
ROMless
Ram Size
32K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Data Converters
A/D 8x10b; D/A 2x8b
Oscillator Type
Internal
Operating Temperature
-20°C ~ 70°C
Package / Case
176-LQFP
No. Of I/o's
109
Ram Memory Size
32KB
Cpu Speed
120MHz
Digital Ic Case Style
LQFP
Supply Voltage Range
3V To 3.6V
Operating Temperature Range
-20°C To +70°C
Embedded Interface Type
I2C, SSI
Rohs Compliant
Yes
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
R0K572011S000BE - KIT STARTER FOR SH7201HS0005KCU11H - EMULATOR E10A-USB H8S(X),SH2(A)
Eeprom Size
-
Program Memory Size
-
Lead Free Status / RoHS Status
Lead free / RoHS Compliant, Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
DS72011RB120FPV
Manufacturer:
Renesas Electronics America
Quantity:
10 000
- Current page: 272 of 1222
- Download datasheet (8Mb)
Section 9 Bus State Controller (BSC)
(4)
(a)
If a 32-bit bus is selected by the external bus width select bits in the CSn control register, A27 to
A2 are enabled as address signals for longword units and A1 and A0 are disabled (fixed low
level). Table 9.7 shows the data alignment corresponding to byte addresses for different data sizes.
Pins WR3 to WR0 are enabled when byte strobe mode (WRMOD = 0) is selected. Pins BC3 to
BC0 are not used.
Only the WR3 pin is enabled when one-write strobe mode (WRMOD = 1) is selected. A low-level
signal is output from the WR3 pin during write access, regardless of the data size. At this time
pins WR2 to WR0 are disabled (fixed high level). The valid byte positions are indicated by pins
BC3 to BC0.
Table 9.7
Note: The valid bits in the data bus for each data size are indicated by circles (O).
Page 244 of 1190
Data Size
Byte
Word
Longword
Access Type and Data Alignment
32-Bit Bus Channel
Crosses (×) indicate bus data bits that are undefined.
Data Alignment (32-Bit Bus Channel)
Byte Address
(Lower 2 Bits) [31:24] [23:16] [15:8] [7:0]
0
1
2
3
0
2
0
O
×
×
×
O
×
O
×
O
×
×
O
×
O
DATA
×
×
O
×
×
O
O
×
×
×
O
×
O
O
[3]
L
H
H
H
L
H
L
[2]
H
L
H
H
L
H
L
R01UH0026EJ0300 Rev. 3.00
WR/BC
[1]
H
H
L
H
H
L
L
SH7201 Group
Sep 24, 2010
[0]
H
H
H
L
H
L
L
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