DS72011RB120FPV Renesas Electronics America, DS72011RB120FPV Datasheet - Page 362

• Manufacturer Part Number: DS72011RB120FPV
• Description: IC SH7201 MPU ROMLESS 176LQFP
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7200r

Specifications of DS72011RB120FPV

• Core Size: 32-Bit
• Core Processor: SH-2A
• Speed: 120MHz
• Connectivity: CAN, EBI/EMI, FIFO, I²C, SCI, Serial Sound
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 104
• Program Memory Type: ROMless
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 70°C
• Package / Case: 176-LQFP
• No. Of I/o's: 109
• Ram Memory Size: 32KB
• Cpu Speed: 120MHz
• Digital Ic Case Style: LQFP
• Supply Voltage Range: 3V To 3.6V
• Operating Temperature Range: -20°C To +70°C
• Embedded Interface Type: I2C, SSI
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: R0K572011S000BE - KIT STARTER FOR SH7201HS0005KCU11H - EMULATOR E10A-USB H8S(X),SH2(A)
• Eeprom Size: -
• Program Memory Size: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant

Section 11 Direct Memory Access Controller (DMAC)
11.3.12 DMA Common Interrupt Control Register (DMICNTA)
DMICNTA determines which channels contribute to the output of a common interrupt request
signal.
Note: Bits 31 to 24 correspond to channel 0 to 7, respectively (31: channel 0, 30: channel
Page 334 of 1190
Bit
31 to 24 DINTA
23 to 0
Initial value:
Initial value:
R/W:
R/W:
1, …, 24: channel 7).
Bit:
Bit:
Bit Name
⎯
R/W
31
15
—
R
0
0
R/W
30
14
—
R
0
0
R/W
29
13
—
R
0
0
All 0
Initial
Value
All 0
R/W
28
12
—
R
0
0
DINTA
R/W
27
11
—
R
0
0
R/W
R/W
R
R/W
26
10
—
R
0
0
Description
DMA Common Interrupt Request Signal Control
These bits are used to determine which channels
contribute to the output of a common interrupt request
signal.
Channels for which the DINTA bit is set to "1"
contribute to the output of a common interrupt request
signal.
Channels for which the DINTA bit is cleared to "0" do
not contribute to the output of a common interrupt
request signal.
Only the states of channels for which the
corresponding DINTA bit is set to "1" are reflected in
the DMA interrupt status register (DMISTS) when a
common interrupt request signal has been generated.
For details, see section 11.5.2, DMA Interrupt
Requests.
0: The channel does not contribute to the output of a
1: The channel contributes to the output of a common
Reserved
These bits are always read as 0. The write value
should always be 0.
R/W
25
—
R
0
9
0
interrupt request
common interrupt requests
R/W
24
—
R
0
8
0
23
—
—
R
R
0
7
0
22
—
—
R
R
0
6
0
21
—
—
R
R
0
5
0
20
—
—
R
R
0
4
0
R01UH0026EJ0300 Rev. 3.00
19
—
—
R
R
0
3
0
18
—
—
R
R
0
2
0
SH7201 Group
17
—
Sep 24, 2010
—
R
R
0
1
0
16
—
—
R
R
0
0
0