DS72011RB120FPV Renesas Electronics America, DS72011RB120FPV Datasheet - Page 914
![IC SH7201 MPU ROMLESS 176LQFP](/photos/28/61/286154/176-lqfp_sml.jpg)
DS72011RB120FPV
Manufacturer Part Number
DS72011RB120FPV
Description
IC SH7201 MPU ROMLESS 176LQFP
Manufacturer
Renesas Electronics America
Series
SuperH® SH7200r
Datasheet
1.R0K572011S000BE.pdf
(1222 pages)
Specifications of DS72011RB120FPV
Core Size
32-Bit
Core Processor
SH-2A
Speed
120MHz
Connectivity
CAN, EBI/EMI, FIFO, I²C, SCI, Serial Sound
Peripherals
DMA, POR, PWM, WDT
Number Of I /o
104
Program Memory Type
ROMless
Ram Size
32K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Data Converters
A/D 8x10b; D/A 2x8b
Oscillator Type
Internal
Operating Temperature
-20°C ~ 70°C
Package / Case
176-LQFP
No. Of I/o's
109
Ram Memory Size
32KB
Cpu Speed
120MHz
Digital Ic Case Style
LQFP
Supply Voltage Range
3V To 3.6V
Operating Temperature Range
-20°C To +70°C
Embedded Interface Type
I2C, SSI
Rohs Compliant
Yes
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
R0K572011S000BE - KIT STARTER FOR SH7201HS0005KCU11H - EMULATOR E10A-USB H8S(X),SH2(A)
Eeprom Size
-
Program Memory Size
-
Lead Free Status / RoHS Status
Lead free / RoHS Compliant, Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
DS72011RB120FPV
Manufacturer:
Renesas Electronics America
Quantity:
10 000
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Section 20 A/D Converter (ADC)
20.4
The A/D converter uses the successive-approximation method, and the resolution is 10 bits. It has
three operating modes: single mode, multi mode, and scan mode. Switching the operating mode or
analog input channels must be done while the ADST bit in ADCSR is 0 to prevent incorrect
operation. The ADST bit can be set at the same time as the operating mode or analog input
channels are changed.
20.4.1
Single mode should be selected when only A/D conversion on one channel is required.
In single mode, A/D conversion is performed once for the specified one analog input channel, as
follows:
1. A/D conversion for the selected channel starts when the ADST bit in ADCSR is set to 1 by
2. When A/D conversion is completed, the A/D conversion result is transferred to the A/D data
3. After A/D conversion has completed, the ADF bit in ADCSR is set to 1. If the ADIE bit is set
4. The ADST bit that remains 1 during A/D conversion is automatically cleared to 0 when A/D
When the operating mode or analog input channel selection must be changed during A/D
conversion, to prevent incorrect operation, first clear the ADST bit to 0 to halt A/D conversion.
After making the necessary changes, set the ADST bit to 1 to start A/D conversion again. The
ADST bit can be set at the same time as the mode or channel selection is switched.
Page 886 of 1190
software, MTU2, TMR, or external trigger input.
register corresponding to the channel.
to 1 at this time, an ADI interrupt request is generated.
conversion is completed, and the A/D converter becomes idle.
Operation
Single Mode
R01UH0026EJ0300 Rev. 3.00
SH7201 Group
Sep 24, 2010
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