EZ80F91NA050SC Zilog, EZ80F91NA050SC Datasheet - Page 121

• Manufacturer Part Number: EZ80F91NA050SC
• Description: IC ACCLAIM MCU 256KB 144-BGA
• Manufacturer: Zilog
• Series: eZ80® Acclaim!®r

Specifications of EZ80F91NA050SC

• Core Processor: Z8
• Core Size: 8-Bit
• Speed: 50MHz
• Connectivity: Ethernet, I²C, IrDA, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 32
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Oscillator Type: Internal
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 144-LBGA
• Data Bus Width: 8 bit
• Maximum Clock Frequency: 50 MHz
• Data Ram Size: 16 KB
• Number Of Programmable I/os: 32
• Number Of Timers: 16 Bit
• Operating Supply Voltage: 3 V to 3.6 V
• Mounting Style: SMD/SMT
• Height: 1.5 mm
• Length: 13 mm
• Maximum Operating Temperature: + 70 C
• Minimum Operating Temperature: 0 C
• Width: 13 mm
• For Use With: 269-4712 - KIT DEV ENCORE 32 SERIES269-4671 - BOARD ZDOTS SBC Z80ACCLAIM PLUS269-4561 - KIT DEV FOR EZ80F91 W/C-COMPILER269-4560 - KIT DEV FOR EZ80F91 W/C-COMPILER
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: No RoHS Version Available
• Other names: 269-3251

PS019215-0910
Flash Column Select Register
The Flash Column Select Register is an 8-bit value used to define one of the 256 bytes of
Flash memory contained in a single row. This register is used for all I/O access to Flash
memory. In addition, each access to the FLASH_DATA register causes an autoincrement
of the Flash address stored in the Flash Address registers (FLASH_PAGE, FLASH_ROW,
FLASH_COL). See
Table 45. Flash Column Select Register
Flash Program Control Register
The Flash Program Control Register is used to perform the functions of MASS ERASE,
PAGE ERASE, and ROW PROGRAM. MASS ERASE and PAGE ERASE are 
self-clearing functions.
MASS ERASE requires approximately 200 ms to completely erase the full 256 KB of
main Flash and the 512-byte information page if the FLASH_PAGE register(0x00FC)
bit7(INFO_EN) is set. The 200 ms time is not reduced by excluding the 512 byte
information page from erasing.
PAGE ERASE requires approximately 10 ms to erase a 2 KB page.
On completion of either a MASS ERASE or PAGE ERASE, the value of each 
corresponding bit is reset to 0.
When Flash is being erased, any Read or Write access to Flash forces the CPU into a Wait
state until the Erase operation is complete and the Flash is accessed. Reads and Writes to
areas other than Flash memory proceeds as usual while an Erase operation is 
underway.
During row programming, any reads of Flash memory force a WAIT condition until the
row programming operation completes or times out. See
Bit
Reset
CPU Access
Note: R/W = Read/Write, R = Read Only.
Bit 
Position
[7:0]
FLASH_COL
Value
00h–FFh Column address of Flash memory to be used during an I/O
Table
R/W
45.
7
0
Description
access of Flash memory.
R/W
6
0
R/W
5
0
(FLASH_COL = 00FEh)
R/W
4
0
Table 46
R/W
3
0
Product Specification
on page 113.
R/W
2
0
eZ80F91 MCU
R/W
1
0
Flash Memory
R/W
0
0
112