EZ80F91NA050SC Zilog, EZ80F91NA050SC Datasheet - Page 311

• Manufacturer Part Number: EZ80F91NA050SC
• Description: IC ACCLAIM MCU 256KB 144-BGA
• Manufacturer: Zilog
• Series: eZ80® Acclaim!®r

Specifications of EZ80F91NA050SC

• Core Processor: Z8
• Core Size: 8-Bit
• Speed: 50MHz
• Connectivity: Ethernet, I²C, IrDA, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 32
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Oscillator Type: Internal
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 144-LBGA
• Data Bus Width: 8 bit
• Maximum Clock Frequency: 50 MHz
• Data Ram Size: 16 KB
• Number Of Programmable I/os: 32
• Number Of Timers: 16 Bit
• Operating Supply Voltage: 3 V to 3.6 V
• Mounting Style: SMD/SMT
• Height: 1.5 mm
• Length: 13 mm
• Maximum Operating Temperature: + 70 C
• Minimum Operating Temperature: 0 C
• Width: 13 mm
• For Use With: 269-4712 - KIT DEV ENCORE 32 SERIES269-4671 - BOARD ZDOTS SBC Z80ACCLAIM PLUS269-4561 - KIT DEV FOR EZ80F91 W/C-COMPILER269-4560 - KIT DEV FOR EZ80F91 W/C-COMPILER
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: No RoHS Version Available
• Other names: 269-3251

Table 184. EMAC Configuration Register 3
PS019215-0910
Bit
Reset
CPU Access
Note: R/W = Read/Write.
Bit 
Position
7
LONGP
6
PUREP
5
XSDFR
4
BITMD
[3:0]
RETRY
Note: IEEE 802.3 specifies a minimum of 56 bits of preamble. A maximum number of bits is not de-
fined. For details, see the IEEE 802.3 Specification, Section 7.2.3.2.
EMAC Configuration Register 3
The EMAC Configuration Register 3 controls preamble length and value, excessive defer-
ment, and the number of retransmission tries. See
Value
0
1
0
1
0
1
0
1
0h–Fh
Description
The EMAC allows any preamble length as per the IEEE 802.3
specification.*
The EMAC only allows Receive packets that contain preamble
fields less than 12 bytes in length.*
No preamble error checking is performed.
The EMAC verifies the content of the preamble to ensure that it
contains a value of 55h and that it is error-free. Packets
containing an errored preamble are discarded.
The EMAC aborts when the excessive deferral limit is reached.
The EMAC defers to the carrier indefinitely as per the IEEE
802.3 specification.
Disable 10 Mbps ENDEC mode.
Enable 10 Mbps ENDEC mode.
A programmable field specifying the number of retransmission
attempts following a collision before aborting the packet due to
excessive collisions.
R/W
7
0
R/W
6
0
R/W
5
0
(EMAC_CFG3 = 0023h)
R/W
4
0
R/W
3
1
Table
R/W
2
1
184.
R/W
Ethernet Media Access Controller
1
1
Product Specification
R/W
0
1
302