EZ80F91NA050SC Zilog, EZ80F91NA050SC Datasheet - Page 142

• Manufacturer Part Number: EZ80F91NA050SC
• Description: IC ACCLAIM MCU 256KB 144-BGA
• Manufacturer: Zilog
• Series: eZ80® Acclaim!®r

Specifications of EZ80F91NA050SC

• Core Processor: Z8
• Core Size: 8-Bit
• Speed: 50MHz
• Connectivity: Ethernet, I²C, IrDA, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 32
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Oscillator Type: Internal
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 144-LBGA
• Data Bus Width: 8 bit
• Maximum Clock Frequency: 50 MHz
• Data Ram Size: 16 KB
• Number Of Programmable I/os: 32
• Number Of Timers: 16 Bit
• Operating Supply Voltage: 3 V to 3.6 V
• Mounting Style: SMD/SMT
• Height: 1.5 mm
• Length: 13 mm
• Maximum Operating Temperature: + 70 C
• Minimum Operating Temperature: 0 C
• Width: 13 mm
• For Use With: 269-4712 - KIT DEV ENCORE 32 SERIES269-4671 - BOARD ZDOTS SBC Z80ACCLAIM PLUS269-4561 - KIT DEV FOR EZ80F91 W/C-COMPILER269-4560 - KIT DEV FOR EZ80F91 W/C-COMPILER
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: No RoHS Version Available
• Other names: 269-3251

PS019215-0910
Timer Interrupt Enable Register
The Timer x Interrupt Enable Register (see
operations. Only bits related to functions present in a given timer are active.
Table 55. Timer Interrupt Enable
TMR2_IER = 0070h, TMR3_IER = 0075h)
1
RLD
0
TIM_EN
Bit
Reset
CPU Access
Note: R = Read only; R/W = Read/Write.
Bit
Position
7
6
IRQ_OC3_EN
5
IRQ_OC2_EN
4
IRQ_OC1_EN
3
IRQ_OC0_EN
0
1
0
1
Value
0
0
1
0
1
0
1
0
1
Reload function is not forced.
Force reload. When 1 is written to this bit, the values in the
reload registers are loaded into the downcounter.
The programmable reload timer is disabled.
The programmable reload timer is enabled.
R/W
Description
Unused.
Interrupt requests for OC3 are disabled (valid only in
OUTPUT COMPARE mode). OC operations occur in Timer 3.
Interrupt requests for OC3 are enabled (valid only in OUTPUT
COMPARE mode). OC operations occur in Timer 3.
Interrupt requests for OC2 are disabled (valid only in
OUTPUT COMPARE mode). OC operations occur in Timer 3.
Interrupt requests for OC2 are enabled (valid only in OUTPUT
COMPARE mode). OC operations occur in Timer 3.
Interrupt requests for OC1 are disabled (valid only in
OUTPUT COMPARE mode). OC operations occur in Timer 3.
Interrupt requests for OC1 are enabled (valid only in OUTPUT
COMPARE mode). OC operations occur in Timer 3.
Interrupt requests for OC0 are disabled (valid only in
OUTPUT COMPARE mode). OC operations occur in Timer 3.
Interrupt requests for OC0 are enabled (valid only in OUTPUT
COMPARE mode). OC operations occur in Timer 3.
7
0
R/W
6
0
(TMR0_IER = 0061h, TMR1_IER = 0066h,
R/W
Table
5
0
55) is used to control timer interrupt
R/W
4
0
R/W
3
0
Programmable Reload Timers
Product Specification
R/W
2
0
eZ80F91 MCU
R/W
1
0
R/W
0
0
133