EZ80F91NA050SC Zilog, EZ80F91NA050SC Datasheet - Page 98

• Manufacturer Part Number: EZ80F91NA050SC
• Description: IC ACCLAIM MCU 256KB 144-BGA
• Manufacturer: Zilog
• Series: eZ80® Acclaim!®r

Specifications of EZ80F91NA050SC

• Core Processor: Z8
• Core Size: 8-Bit
• Speed: 50MHz
• Connectivity: Ethernet, I²C, IrDA, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 32
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Oscillator Type: Internal
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 144-LBGA
• Data Bus Width: 8 bit
• Maximum Clock Frequency: 50 MHz
• Data Ram Size: 16 KB
• Number Of Programmable I/os: 32
• Number Of Timers: 16 Bit
• Operating Supply Voltage: 3 V to 3.6 V
• Mounting Style: SMD/SMT
• Height: 1.5 mm
• Length: 13 mm
• Maximum Operating Temperature: + 70 C
• Minimum Operating Temperature: 0 C
• Width: 13 mm
• For Use With: 269-4712 - KIT DEV ENCORE 32 SERIES269-4671 - BOARD ZDOTS SBC Z80ACCLAIM PLUS269-4561 - KIT DEV FOR EZ80F91 W/C-COMPILER269-4560 - KIT DEV FOR EZ80F91 W/C-COMPILER
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: No RoHS Version Available
• Other names: 269-3251

PS019215-0910
Bit 
Position
[3:0]
BUS_CYCLE
Notes
1. Setting the BUS_CYCLE to 1 in Intel bus mode causes the ALE pin to not function properly.
2. Use of the external WAIT input pin in Z80 mode requires that BUS_CYCLE is set to a value
3. BUS_CYCLE produces no effect in eZ80 mode.
greater than 1.
Bus Arbiter
The Bus Arbiter within the eZ80F91 allows external bus masters to gain control of the
CPU memory interface bus. During normal operation, the eZ80F91 device is the bus mas-
ter. External devices request master use of the bus by asserting the BUSREQ pin. The Bus
Arbiter forces the CPU to release the bus after completing the current instruction. When
the CPU releases the bus, the Bus Arbiter asserts the BUSACK pin to notify the external
device that it can master the bus. When an external device assumes control of the memory
interface bus, the bus acknowledge cycle is complete.
of the pins on the eZ80F91 device during bus acknowledge cycles.
During a bus acknowledge cycle, the bus interface pins of the eZ80F91 device are used by
an external bus master to control the memory and I/O chip selects.
Value Description
0000
0001
0010
0011
0100
0101
0110
0111
1000
1001
1010
1011
1100
1101
1110
1111
Not valid.
Each bus mode state is 1 eZ80
Each bus mode state is 2 eZ80 clock cycles in duration.
Each bus mode state is 3 eZ80 clock cycles in duration.
Each bus mode state is 4 eZ80 clock cycles in duration.
Each bus mode state is 5 eZ80 clock cycles in duration.
Each bus mode state is 6 eZ80 clock cycles in duration.
Each bus mode state is 7 eZ80 clock cycles in duration.
Each bus mode state is 8 eZ80 clock cycles in duration.
Each bus mode state is 9 eZ80 clock cycles in duration.
Each bus mode state is 10 eZ80 clock cycles in duration.
Each bus mode state is 11 eZ80 clock cycles in duration.
Each bus mode state is 12 eZ80 clock cycles in duration.
Each bus mode state is 13 eZ80 clock cycles in duration.
Each bus mode state is 14 eZ80 clock cycles in duration.
Each bus mode state is 15 eZ80 clock cycles in duration.
®
clock cycle in duration.
Table 31
on page 90 lists the status
Chip Selects and Wait States
Product Specification
1, 2, 3
eZ80F91 MCU
89