EZ80F91NA050SC Zilog, EZ80F91NA050SC Datasheet - Page 188

• Manufacturer Part Number: EZ80F91NA050SC
• Description: IC ACCLAIM MCU 256KB 144-BGA
• Manufacturer: Zilog
• Series: eZ80® Acclaim!®r

Specifications of EZ80F91NA050SC

• Core Processor: Z8
• Core Size: 8-Bit
• Speed: 50MHz
• Connectivity: Ethernet, I²C, IrDA, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 32
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Oscillator Type: Internal
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 144-LBGA
• Data Bus Width: 8 bit
• Maximum Clock Frequency: 50 MHz
• Data Ram Size: 16 KB
• Number Of Programmable I/os: 32
• Number Of Timers: 16 Bit
• Operating Supply Voltage: 3 V to 3.6 V
• Mounting Style: SMD/SMT
• Height: 1.5 mm
• Length: 13 mm
• Maximum Operating Temperature: + 70 C
• Minimum Operating Temperature: 0 C
• Width: 13 mm
• For Use With: 269-4712 - KIT DEV ENCORE 32 SERIES269-4671 - BOARD ZDOTS SBC Z80ACCLAIM PLUS269-4561 - KIT DEV FOR EZ80F91 W/C-COMPILER269-4560 - KIT DEV FOR EZ80F91 W/C-COMPILER
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: No RoHS Version Available
• Other names: 269-3251

PS019215-0910
UART Recommended Usage
An interrupt due to one of the above conditions is cleared when the UARTx_LSR register
is read. In case of FIFO mode, a line status interrupt is generated only after the received
byte with an error reaches the top of the FIFO and is ready to be read.
A line status interrupt is activated (provided this interrupt is enabled) as long as the Read
pointer of the receiver FIFO points to the location of the FIFO that contains a byte with the
error. The interrupt is immediately cleared when the UARTx_LSR register is read. The
ERR bit of the UARTx_LSR register is active as long as an erroneous byte is present in the
receiver FIFO.
UART Modem Status Interrupt
The modem status interrupt is generated if there is any change in state of the modem status
inputs to the UART. This interrupt is cleared when the CPU reads the UARTx_MSR regis-
ter.
The following standard sequence of events occurs in the UART block of the eZ80F91
device. A description of each follows.
•
•
•
Module Reset
Upon reset, all internal registers are set to their default values. All command status regis-
ters are programmed with their default values, and the FIFOs are flushed.
Control Transfers to Configure UART Operation
Based on the requirements of the application, the data transfer baud rate is determined and
the BRG is configured to generate a 16X clock frequency. Interrupts are disabled and the
communication control parameters are programmed in the UARTx_LCTL register. The
FIFO configuration is determined and the receive trigger levels are set in the
UARTx_FCTL register. The status registers, UARTx_LSR and UARTx_MSR, are read to
ensure that none of the interrupt sources are active. The interrupts are enabled (except for
the transmit interrupt) and the application is ready to use the module for transmission/
reception.
Data Transfers
Transmit—
immediately expected in response. The application reads the UARTx_IIR register and
determines whether the interrupt occurs due to either an empty UARTx_THR register or a
Module Reset
Control Transfers to Configure UART Operation
Data Transfers
To transmit data, the application enables the transmit interrupt. An interrupt is
Universal Asynchronous Receiver/Transmitter
Product Specification
eZ80F91 MCU
179