EZ80F91NA050SC Zilog, EZ80F91NA050SC Datasheet - Page 250

• Manufacturer Part Number: EZ80F91NA050SC
• Description: IC ACCLAIM MCU 256KB 144-BGA
• Manufacturer: Zilog
• Series: eZ80® Acclaim!®r

Specifications of EZ80F91NA050SC

• Core Processor: Z8
• Core Size: 8-Bit
• Speed: 50MHz
• Connectivity: Ethernet, I²C, IrDA, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 32
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Oscillator Type: Internal
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 144-LBGA
• Data Bus Width: 8 bit
• Maximum Clock Frequency: 50 MHz
• Data Ram Size: 16 KB
• Number Of Programmable I/os: 32
• Number Of Timers: 16 Bit
• Operating Supply Voltage: 3 V to 3.6 V
• Mounting Style: SMD/SMT
• Height: 1.5 mm
• Length: 13 mm
• Maximum Operating Temperature: + 70 C
• Minimum Operating Temperature: 0 C
• Width: 13 mm
• For Use With: 269-4712 - KIT DEV ENCORE 32 SERIES269-4671 - BOARD ZDOTS SBC Z80ACCLAIM PLUS269-4561 - KIT DEV FOR EZ80F91 W/C-COMPILER269-4560 - KIT DEV FOR EZ80F91 W/C-COMPILER
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: No RoHS Version Available
• Other names: 269-3251

Table 134. ZDI Read Only Registers (Continued)
Table 135. ZDI Address Match Registers
PS019215-0910
ZDI Address
03h
10h
11h
12h
17h
20h
Bit
Reset
CPU Access
Note: W = Write Only.
Bit 
Position
[7:0]
zdi_addrx_l,
zdi_addrx_h,
or 
zdi_addrx_u
ZDI Register Definitions
ZDI Address Match Registers
The four sets of address match registers are used for setting the addresses for generating
break points. When the accompanying BRK_ADDRX bit is set in the ZDI Break Control
register to enable the particular address match, the current eZ80F91 address is compared
with the 3-byte address set, {ZDI_ADDRx_U, ZDI_ADDRx_H, and ZDI_ADDR_x_L}.
If the CPU is operating in ADL mode, the address is supplied by ADDR[23:0]. If the CPU
is operating in Z80
match is found, ZDI issues a break to the eZ80F91 device placing the CPU in ZDI mode
pending further instructions from the ZDI interface block. If the address is not the first op-
code fetch, the ZDI break is executed at the end of the instruction in which it is executed.
There are four sets of address match registers. They are used in conjunction with each
other to break on branching instructions. See
ZDI Register Name
ZDI_STAT
ZDI_RD_L
ZDI_RD_H
ZDI_RD_U
ZDI_BUS_STAT
ZDI_RD_MEM
Value
00h–FFh The four sets of ZDI address match registers are used for
W
X
7
Description
setting the addresses for generating break points. The 24
bit addresses are supplied by {ZDI_ADDRx_U,
ZDI_ADDRx_H, ZDI_ADDRx_L, where x is 0, 1, 2, or 3.
®
W
X
6
mode, the address is supplied by {MBASE[7:0], ADDR[15:0]}. If a
W
X
5
Status Register
Read Memory Address Low Byte Register
Read Memory Address High Byte Register
Read Memory Address Upper Byte Register
Bus Status Register
Read Memory Data Value
ZDI Register Function
W
X
4
W
X
3
Table 135
W
X
2
on page 241.
W
X
1
Product Specification
W
X
0
Zilog Debug Interface
eZ80F91 MCU
Reset
Value
00h
XXh
XXh
XXh
00h
XXh
241