EZ80F91NA050SC Zilog, EZ80F91NA050SC Datasheet - Page 280

• Manufacturer Part Number: EZ80F91NA050SC
• Description: IC ACCLAIM MCU 256KB 144-BGA
• Manufacturer: Zilog
• Series: eZ80® Acclaim!®r

Specifications of EZ80F91NA050SC

• Core Processor: Z8
• Core Size: 8-Bit
• Speed: 50MHz
• Connectivity: Ethernet, I²C, IrDA, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 32
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Oscillator Type: Internal
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 144-LBGA
• Data Bus Width: 8 bit
• Maximum Clock Frequency: 50 MHz
• Data Ram Size: 16 KB
• Number Of Programmable I/os: 32
• Number Of Timers: 16 Bit
• Operating Supply Voltage: 3 V to 3.6 V
• Mounting Style: SMD/SMT
• Height: 1.5 mm
• Length: 13 mm
• Maximum Operating Temperature: + 70 C
• Minimum Operating Temperature: 0 C
• Width: 13 mm
• For Use With: 269-4712 - KIT DEV ENCORE 32 SERIES269-4671 - BOARD ZDOTS SBC Z80ACCLAIM PLUS269-4561 - KIT DEV FOR EZ80F91 W/C-COMPILER269-4560 - KIT DEV FOR EZ80F91 W/C-COMPILER
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: No RoHS Version Available
• Other names: 269-3251

Table 155. PLL Control Register 1
.
PS019215-0910
Bit
Reset
CPU Access
Note: R = Read Only; R/W = Read/Write.
Bit 
Position
[7:6]
5
LCK_STATUS
4 
INT_LOCK
3
INT_UNLOCK
2
INT_LOCK_EN
1
INT_UNLOCK_
EN
0
PLL_ENABLE
Note
1. PLL cannot be disabled if the CLK_MUX bit of PLL_CTL0[1:0] is set to 01, because the PLL is
selected as the clock source.
Value Description
00
0
1
0
1
0
1
0
1
0
1
0
1
Reserved.
PLL is currently out of lock.
PLL is currently locked.
Lock signal from PLL has not risen since last time register was
read.
Interrupt generated when PLL enters LOCK mode. Held until
register is read.
Lock signal from PLL has not fallen since last time register was
read.
Interrupt generated when PLL goes out of lock. Held until
register is read.
Interrupt generation for PLL locked condition (Bit 4) is disabled.
Interrupt generation for PLL locked condition is enabled.
Interrupt generation for PLL unlocked condition (Bit 3) is
disabled.
Interrupt generation for PLL unlocked condition is enabled.
PLL is disabled.
PLL is enabled.
R
7
0
R
6
0
(PLL_CTL1 = 005Fh)
1
R
5
0
R/W
4
0
R/W
3
0
R/W
2
0
R/W
1
0
Product Specification
R/W
0
0
Phase-Locked Loop
eZ80F91 MCU
271