EZ80F91NA050SC Zilog, EZ80F91NA050SC Datasheet - Page 32
EZ80F91NA050SC
Manufacturer Part Number
EZ80F91NA050SC
Description
IC ACCLAIM MCU 256KB 144-BGA
Manufacturer
Zilog
Series
eZ80® Acclaim!®r
Specifications of EZ80F91NA050SC
Core Processor
Z8
Core Size
8-Bit
Speed
50MHz
Connectivity
Ethernet, I²C, IrDA, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
32
Program Memory Size
256KB (256K x 8)
Program Memory Type
FLASH
Ram Size
16K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Oscillator Type
Internal
Operating Temperature
0°C ~ 70°C
Package / Case
144-LBGA
Data Bus Width
8 bit
Maximum Clock Frequency
50 MHz
Data Ram Size
16 KB
Number Of Programmable I/os
32
Number Of Timers
16 Bit
Operating Supply Voltage
3 V to 3.6 V
Mounting Style
SMD/SMT
Height
1.5 mm
Length
13 mm
Maximum Operating Temperature
+ 70 C
Minimum Operating Temperature
0 C
Width
13 mm
For Use With
269-4712 - KIT DEV ENCORE 32 SERIES269-4671 - BOARD ZDOTS SBC Z80ACCLAIM PLUS269-4561 - KIT DEV FOR EZ80F91 W/C-COMPILER269-4560 - KIT DEV FOR EZ80F91 W/C-COMPILER
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Eeprom Size
-
Data Converters
-
Lead Free Status / Rohs Status
No RoHS Version Available
Other names
269-3251
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
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PS019215-0910
Table 2. Pin Identification on the eZ80F91 Device (Continued)
LQFP
Pin No
127
128
129
130
131
132
133
134
135
136
BGA
Pin No Symbol
C7
D7
A6
B6
C6
E7
A5
B5
D6
C5
TxD2
TxD1
TxD0
Tx_EN
Tx_CLK
Tx_ER
V
V
Rx_ER
Rx_CLK
DD
SS
Function
MII Transmit
Data
MII Transmit
Data
MII Transmit
Data
MII Transmit
Enable
MII Transmit
Clock
MII Transmit
Error
Power Supply
Ground
MII Receive
Error
MII Receive
Clock
Signal Direction Description
Output
Output
Output
Output
Input
Output
Input
Input
This pin is used by the Ethernet MAC
for the MII Interface to the PHY.
Transmit Data is synchronous to the
rising-edge of Tx_CLK.
This pin is used by the Ethernet MAC
for the MII Interface to the PHY.
Transmit Data is synchronous to the
rising-edge of Tx_CLK.
This pin is used by the Ethernet MAC
for the MII Interface to the PHY.
Transmit Data is synchronous to the
rising-edge of Tx_CLK.
This pin is used by the Ethernet MAC
for the MII Interface to the PHY.
Transmit Enable is synchronous to the
rising-edge of Tx_CLK.
This pin is used by the Ethernet MAC
for the MII Interface to the PHY.
Transmit Clock is the Nibble or
Symbol Clock provided by the MII
PHY interface.
This pin is used by the Ethernet MAC
for the MII Interface to the PHY.
Transmit Error is synchronous to the
rising-edge of Tx_CLK.
Power Supply.
Ground.
This pin is used by the Ethernet MAC
for the MII Interface to the PHY.
Receive Error is provided by the MII
PHY interface synchronous to the
rising-edge of Rx_CLK.
This pin is used by the Ethernet MAC
for the MII Interface to the PHY.
Receive Clock is the Nibble or Symbol
Clock provided by the MII PHY
interface.
Product Specification
Architectural Overview
23
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