EZ80F91NA050SC Zilog, EZ80F91NA050SC Datasheet - Page 22
EZ80F91NA050SC
Manufacturer Part Number
EZ80F91NA050SC
Description
IC ACCLAIM MCU 256KB 144-BGA
Manufacturer
Zilog
Series
eZ80® Acclaim!®r
Specifications of EZ80F91NA050SC
Core Processor
Z8
Core Size
8-Bit
Speed
50MHz
Connectivity
Ethernet, I²C, IrDA, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
32
Program Memory Size
256KB (256K x 8)
Program Memory Type
FLASH
Ram Size
16K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Oscillator Type
Internal
Operating Temperature
0°C ~ 70°C
Package / Case
144-LBGA
Data Bus Width
8 bit
Maximum Clock Frequency
50 MHz
Data Ram Size
16 KB
Number Of Programmable I/os
32
Number Of Timers
16 Bit
Operating Supply Voltage
3 V to 3.6 V
Mounting Style
SMD/SMT
Height
1.5 mm
Length
13 mm
Maximum Operating Temperature
+ 70 C
Minimum Operating Temperature
0 C
Width
13 mm
For Use With
269-4712 - KIT DEV ENCORE 32 SERIES269-4671 - BOARD ZDOTS SBC Z80ACCLAIM PLUS269-4561 - KIT DEV FOR EZ80F91 W/C-COMPILER269-4560 - KIT DEV FOR EZ80F91 W/C-COMPILER
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Eeprom Size
-
Data Converters
-
Lead Free Status / Rohs Status
No RoHS Version Available
Other names
269-3251
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
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PS019215-0910
Table 2. Pin Identification on the eZ80F91 Device (Continued)
LQFP
Pin No
78
79
80
81
82
83
84
85
BGA
Pin No Symbol
K12
K11
H8
J11
J12
J10
G7
H12
PD5
DSR0
PD6
DCD0
PD7
RI0
V
V
LOOP_FILT PLL Loop Filter Analog
PLL_V
X
DD
SS
OUT
SS
Function
GPIO Port D
Data Set
Ready
GPIO Port D
Data Carrier
Detect
GPIO Port D
Ring Indicator Input, Active Low Modem status signal to the UART.
Power Supply
Ground
Ground
System Clock
Oscillator
Output
Signal Direction Description
Bidirectional
Input, Active Low Modem status signal to the UART.
Bidirectional
Input, Active Low Modem status signal to the UART.
Bidirectional
Output
This pin is used for GPIO. It is
individually programmed as input or
output and is also used individually as
an interrupt input. Each Port D pin,
when programmed as output is
selected to be an open-drain or open-
source output. Port D is multiplexed
with one UART.
This signal is multiplexed with PD5.
This pin is used for GPIO. It is
individually programmed as input or
output and is also used individually as
an interrupt input. Each Port D pin,
when programmed as output is
selected to be an open-drain or open-
source output. Port D is multiplexed
with one UART.
This signal is multiplexed with PD6.
This pin is used for GPIO. It is
individually programmed as input or
output and is also used individually as
an interrupt input. Each Port D pin,
when programmed as output is
selected to be an open-drain or open-
source output. Port D is multiplexed
with one UART.
This signal is multiplexed with PD7.
Power Supply.
Ground.
Loop Filter pin for the Analog PLL.
Ground for Analog PLL.
This pin is the output of the onboard
crystal oscillator. When used, a crystal
must be connected between X
X
OUT
.
Product Specification
Architectural Overview
IN
and
13
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