EZ80F91NA050SC Zilog, EZ80F91NA050SC Datasheet - Page 302

• Manufacturer Part Number: EZ80F91NA050SC
• Description: IC ACCLAIM MCU 256KB 144-BGA
• Manufacturer: Zilog
• Series: eZ80® Acclaim!®r

Specifications of EZ80F91NA050SC

• Core Processor: Z8
• Core Size: 8-Bit
• Speed: 50MHz
• Connectivity: Ethernet, I²C, IrDA, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 32
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Oscillator Type: Internal
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 144-LBGA
• Data Bus Width: 8 bit
• Maximum Clock Frequency: 50 MHz
• Data Ram Size: 16 KB
• Number Of Programmable I/os: 32
• Number Of Timers: 16 Bit
• Operating Supply Voltage: 3 V to 3.6 V
• Mounting Style: SMD/SMT
• Height: 1.5 mm
• Length: 13 mm
• Maximum Operating Temperature: + 70 C
• Minimum Operating Temperature: 0 C
• Width: 13 mm
• For Use With: 269-4712 - KIT DEV ENCORE 32 SERIES269-4671 - BOARD ZDOTS SBC Z80ACCLAIM PLUS269-4561 - KIT DEV FOR EZ80F91 W/C-COMPILER269-4560 - KIT DEV FOR EZ80F91 W/C-COMPILER
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: No RoHS Version Available
• Other names: 269-3251

PS019215-0910
•
Figure 60
The Transmit and Receive buffers are subdivided into packet buffers of 32, 64, 128, or 256
bytes in size. The packet buffer size is set in bits 7 and 6 of the EmacBufSize register. An
Ethernet packet accommodate multiple packet buffers. First, however, a brief listing of the
contents of a typical Ethernet packet is in order. See
Table 177. Ethernet Packet Contents
At the start of each packet is a descriptor table that describes the packet. Each actual
Ethernet packet follows the descriptor table as displayed in
Byte Range
Bytes 0–5
Bytes 6–11
Bytes 12–13
Bytes 14–n
Bytes (n+1)–(n+4)
RHBP
TLBP
Receive High Boundary Pointer (RHBP)—this register points to the end of the Receive
buffer + 1.
BP
displays the internal Ethernet shared memory.
Figure 60. Internal Ethernet Shared Memory
Contents
MAC destination address.
MAC source address.
Length/Type field.
MAC Client Data.
Frame Check Sequence.
Rx Buffer
Tx Buffer
Upper Memory Address
Lower Memory Address
Table
177.
Figure 61
Ethernet Media Access Controller
Product Specification
on page 294.
293