EZ80F91NA050SC Zilog, EZ80F91NA050SC Datasheet - Page 63

• Manufacturer Part Number: EZ80F91NA050SC
• Description: IC ACCLAIM MCU 256KB 144-BGA
• Manufacturer: Zilog
• Series: eZ80® Acclaim!®r

Specifications of EZ80F91NA050SC

• Core Processor: Z8
• Core Size: 8-Bit
• Speed: 50MHz
• Connectivity: Ethernet, I²C, IrDA, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 32
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Oscillator Type: Internal
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 144-LBGA
• Data Bus Width: 8 bit
• Maximum Clock Frequency: 50 MHz
• Data Ram Size: 16 KB
• Number Of Programmable I/os: 32
• Number Of Timers: 16 Bit
• Operating Supply Voltage: 3 V to 3.6 V
• Mounting Style: SMD/SMT
• Height: 1.5 mm
• Length: 13 mm
• Maximum Operating Temperature: + 70 C
• Minimum Operating Temperature: 0 C
• Width: 13 mm
• For Use With: 269-4712 - KIT DEV ENCORE 32 SERIES269-4671 - BOARD ZDOTS SBC Z80ACCLAIM PLUS269-4561 - KIT DEV FOR EZ80F91 W/C-COMPILER269-4560 - KIT DEV FOR EZ80F91 W/C-COMPILER
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: No RoHS Version Available
• Other names: 269-3251

eZ80F91 MCU
Product Specification
54
GPIO Interrupts
Each port pin is used as an interrupt source. Interrupts are either level- or edge-triggered.
Level-Triggered Interrupts
When the port is configured for level-triggered interrupts (mode 8), the corresponding port
pin is open-drain. An interrupt request is generated when the level at the pin is the same as
the level stored in the Port x Data register. The port pin value is sampled by the system
clock. The input pin must be held at the selected interrupt level for a minimum of two
clock periods to initiate an interrupt. The interrupt request remains active as long as this
condition is maintained at the external source.
For example, if PA3 is programmed for low-level interrupt and the pin is forced Low for
two clock cycles, an interrupt request signal is generated from that port pin and sent to the
CPU. The interrupt request signal remains active until the external device driving PA3
forces the pin high. The CPU must be enabled to respond to interrupts for the interrupt
request signal to be acted upon.
Edge Triggered Interrupts
When the port is configured for edge triggered interrupts, the corresponding port pin is
open-drain. If the pin receives the correct edge from an external device, the port pin
generates an interrupt request signal to the CPU.
When configured for dual-edge triggered interrupt mode (GPIO mode 6), both a rising and
a falling edge on the pin cause an interrupt request to be sent to the CPU. To select mode 6
from the default mode (mode 2), you must:
1. Set Px_DR = 1
2. Set Px_ALT2 =1
3. Set Px_ALT1= 0
4. Set Px_DDR = 0
When configured for single-edge triggered interrupt mode (GPIO mode 9), the value in
the Port x Data register determines whether a positive or negative edge causes an interrupt
request. 0 in the Port x Data register bit sets the selected pin to generate an interrupt
request for falling edges. 1 in the Port x Data register bit sets the selected pin to generate
an interrupt request for rising edges. To select mode 9 from the default mode (mode 2),
you must:
1. Set Px_DR = 1
2. Set Px_ALT2 = 1
3. Set Px_ALT = 1
4. Set Px_DDR = 1
PS019215-0910
General-Purpose Input/Output