EZ80F91NA050SC Zilog, EZ80F91NA050SC Datasheet - Page 160

• Manufacturer Part Number: EZ80F91NA050SC
• Description: IC ACCLAIM MCU 256KB 144-BGA
• Manufacturer: Zilog
• Series: eZ80® Acclaim!®r

Specifications of EZ80F91NA050SC

• Core Processor: Z8
• Core Size: 8-Bit
• Speed: 50MHz
• Connectivity: Ethernet, I²C, IrDA, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 32
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Oscillator Type: Internal
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 144-LBGA
• Data Bus Width: 8 bit
• Maximum Clock Frequency: 50 MHz
• Data Ram Size: 16 KB
• Number Of Programmable I/os: 32
• Number Of Timers: 16 Bit
• Operating Supply Voltage: 3 V to 3.6 V
• Mounting Style: SMD/SMT
• Height: 1.5 mm
• Length: 13 mm
• Maximum Operating Temperature: + 70 C
• Minimum Operating Temperature: 0 C
• Width: 13 mm
• For Use With: 269-4712 - KIT DEV ENCORE 32 SERIES269-4671 - BOARD ZDOTS SBC Z80ACCLAIM PLUS269-4561 - KIT DEV FOR EZ80F91 W/C-COMPILER269-4560 - KIT DEV FOR EZ80F91 W/C-COMPILER
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: No RoHS Version Available
• Other names: 269-3251

PS019215-0910
Note:
System Clock
TMR3_Count
Clock Enable
PWM0
PWM0
setting of 0000b represents a delay of 0 system clock periods and a setting of 1111b rep-
resents a delay of 15 system clock periods. The PWM delay feature is displayed in
Figure 34
The PWM nonoverlapping delay time must always be defined to be less than the delay
between the rising and falling edges (and the delay between the falling and rising edges)
of all Multi-PWM outputs. In other words, a rising (falling) edge cannot be delayed
beyond the time at which it is subsequently scheduled to fall (rise).
Table 72. PWM Nonoverlapping Output Addressing
Parameter
Timer clock is SCLK ÷ 4
Timer reload value
PWM0 rising edge
PWM0 falling edge
Prescaler divider = 4
PWM nonoverlapping delay = 3
PWM enable
PWM0 enable
Multi-PWM enable
A
Figure 34. PWM Nonoverlapping Output Delay
with associated addressing listed in
9
8
7
Control Register(s)
{TMR3_RR_H, TMR3_RR_L}
{TMR3_PWM0R_H, TMR3_PWM0R_L}
{TMR3_PWM0F_H, TMR3_PWM0F_L}
TMR3_PWM_CTL2[PWM_DLY]
TMR3_PWM_CTL1[PAIR_EN]
TMR3_PWM_CTL1[PWM0_EN]
TMR3_PWM_CTL1[MPWN_EN]
TMR3_CTL[CLK_DIV]
TMR3_CTL[CLK_DIV]
3 x SCLK
6
Table
5
72.
4
Programmable Reload Timers
3
Product Specification
3 x SCLK
2
eZ80F91 MCU
0008h
0004h
1
1
1
Value
00b
000Ch
00b
0011b
1
C
151