EZ80F91NA050SC Zilog, EZ80F91NA050SC Datasheet - Page 221

• Manufacturer Part Number: EZ80F91NA050SC
• Description: IC ACCLAIM MCU 256KB 144-BGA
• Manufacturer: Zilog
• Series: eZ80® Acclaim!®r

Specifications of EZ80F91NA050SC

• Core Processor: Z8
• Core Size: 8-Bit
• Speed: 50MHz
• Connectivity: Ethernet, I²C, IrDA, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 32
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Oscillator Type: Internal
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 144-LBGA
• Data Bus Width: 8 bit
• Maximum Clock Frequency: 50 MHz
• Data Ram Size: 16 KB
• Number Of Programmable I/os: 32
• Number Of Timers: 16 Bit
• Operating Supply Voltage: 3 V to 3.6 V
• Mounting Style: SMD/SMT
• Height: 1.5 mm
• Length: 13 mm
• Maximum Operating Temperature: + 70 C
• Minimum Operating Temperature: 0 C
• Width: 13 mm
• For Use With: 269-4712 - KIT DEV ENCORE 32 SERIES269-4671 - BOARD ZDOTS SBC Z80ACCLAIM PLUS269-4561 - KIT DEV FOR EZ80F91 W/C-COMPILER269-4560 - KIT DEV FOR EZ80F91 W/C-COMPILER
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: No RoHS Version Available
• Other names: 269-3251

PS019215-0910
Data Validity
The data on the SDA line must be stable during the High period of the clock. The High or
Low state of the data line changes only when the clock signal on the SCL line is Low, as
displayed in
START and STOP Conditions
Within the I
STOP conditions.
is High, indicating a START condition. A Low-to-High transition on the SDA line while
SCL is High defines a STOP condition.
START and STOP conditions are always generated by the master. The bus is considered to
be busy after a START condition. The bus is considered to be free for a defined time after
a STOP condition.
SDA Signal
SCL Signal
SDA Signal
SCL Signal
2
Figure 44. START and STOP Conditions In I
Figure
C bus protocol, unique situations arise which are defined as START and
START Condition
Figure 44
43.
Figure 43. I
S
Data Valid
Data Line
Stable
displays a High-to-Low transition on the SDA line while SCL
2
C Clock and Data Relationship
Data Allowed
Change of
2
Product Specification
C Protocol
I
STOP Condition
2
C Serial I/O Interface
P
212