EZ80F91NA050SC Zilog, EZ80F91NA050SC Datasheet - Page 372

• Manufacturer Part Number: EZ80F91NA050SC
• Description: IC ACCLAIM MCU 256KB 144-BGA
• Manufacturer: Zilog
• Series: eZ80® Acclaim!®r

Specifications of EZ80F91NA050SC

• Core Processor: Z8
• Core Size: 8-Bit
• Speed: 50MHz
• Connectivity: Ethernet, I²C, IrDA, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 32
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Oscillator Type: Internal
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 144-LBGA
• Data Bus Width: 8 bit
• Maximum Clock Frequency: 50 MHz
• Data Ram Size: 16 KB
• Number Of Programmable I/os: 32
• Number Of Timers: 16 Bit
• Operating Supply Voltage: 3 V to 3.6 V
• Mounting Style: SMD/SMT
• Height: 1.5 mm
• Length: 13 mm
• Maximum Operating Temperature: + 70 C
• Minimum Operating Temperature: 0 C
• Width: 13 mm
• For Use With: 269-4712 - KIT DEV ENCORE 32 SERIES269-4671 - BOARD ZDOTS SBC Z80ACCLAIM PLUS269-4561 - KIT DEV FOR EZ80F91 W/C-COMPILER269-4560 - KIT DEV FOR EZ80F91 W/C-COMPILER
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: No RoHS Version Available
• Other names: 269-3251

DATA5 8
DATA6 8
DATA7 8
DC Characteristics 339
DCD 190, 193
DCD0 13, 198
DCD1 16
DCTS 193
DDCD 193
DDSR 193
Divider, PLL 266
divisor count 206
divisor count, 16-bit 182
DSR 191, 193
DSR0 13, 198
DSR1 16
DTACK 81, 82
DTR 191, 193
DTR0 12, 198
DTR1 15
E
EC0 17, 127, 129, 132
EC1 22, 127, 129, 132
edge-selectable interrupts 55
Edge-Triggered Interrupts 54
EI, Op Code Map 280
EMAC 287
EMAC Address Filter Register 311
EMAC Boundary Pointer Register—Low and High
Bytes 319
EMAC Boundary Pointer Register—Upper Byte
319
EMAC Buffer Size Register 322
EMAC Configuration Register 1 299
EMAC Configuration Register 2 301
EMAC Configuration Register 3 302
EMAC Configuration Register 4 303
EMAC FIFO Data Register—Low and High Bytes
332
EMAC FIFO Flags Register 333
EMAC Functional Description 288
EMAC Hash Table Register 312
PS019215-0910
EMAC Interpacket Gap 306
EMAC Interpacket Gap Overview 306
EMAC Interpacket Gap Register 307
EMAC Interrupt Enable Register 323
EMAC Interrupt Status Register 325
EMAC Interrupts 292
EMAC Maximum Frame Length Register—Low
and High Bytes 309
EMAC memory 288, 289
EMAC MII Management Register 313
EMAC MII Status Register 327
EMAC Non-Back-To-Back IPG Register—Part 1
308
EMAC Non-Back-To-Back IPG Register—Part 2
308
EMAC PHY Address Register 315
EMAC PHY Configuration Data Register—Low
Byte 314
EMAC PHY Read Status Data Register—Low and
High Bytes 326
EMAC PHY Unit Select Address Register 316
EMAC RAM 93, 94, 95, 96
EMAC Receive Blocks Left Register—Low and
High Bytes 330
EMAC Receive High Boundary Pointer Register—
Low and High Bytes 320
EMAC Receive Read Pointer Register—Low and
High Bytes 321
EMAC Receive Write Pointer Register—High Byte
329
EMAC Receive Write Pointer Register—Low Byte
328
EMAC Receiver Interrupts 292
EMAC Registers 297
EMAC Reset Control Register 317
EMAC Shared Memory Organization 292
EMAC Station Address Register 304
EMAC System Interrupts 292
EMAC Test Register 298
EMAC Transmit Lower Boundary Pointer Regis-
ter—Low and High Bytes 318
EMAC Transmit Pause Timer Value Register—
Low and High Bytes 305
EMAC Transmit Polling Timer Register 316
Product Specification
Index
363