EZ80F91NA050SC Zilog, EZ80F91NA050SC Datasheet - Page 371

• Manufacturer Part Number: EZ80F91NA050SC
• Description: IC ACCLAIM MCU 256KB 144-BGA
• Manufacturer: Zilog
• Series: eZ80® Acclaim!®r

Specifications of EZ80F91NA050SC

• Core Processor: Z8
• Core Size: 8-Bit
• Speed: 50MHz
• Connectivity: Ethernet, I²C, IrDA, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 32
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Oscillator Type: Internal
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 144-LBGA
• Data Bus Width: 8 bit
• Maximum Clock Frequency: 50 MHz
• Data Ram Size: 16 KB
• Number Of Programmable I/os: 32
• Number Of Timers: 16 Bit
• Operating Supply Voltage: 3 V to 3.6 V
• Mounting Style: SMD/SMT
• Height: 1.5 mm
• Length: 13 mm
• Maximum Operating Temperature: + 70 C
• Minimum Operating Temperature: 0 C
• Width: 13 mm
• For Use With: 269-4712 - KIT DEV ENCORE 32 SERIES269-4671 - BOARD ZDOTS SBC Z80ACCLAIM PLUS269-4561 - KIT DEV FOR EZ80F91 W/C-COMPILER269-4560 - KIT DEV FOR EZ80F91 W/C-COMPILER
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: No RoHS Version Available
• Other names: 269-3251

Bus Mode Controller 70
bus mode state 71, 72, 75
Bus modes 70
bus modes 71, 84, 88
Bus Modes, Switching Between 84
Bus Requests During ZDI Debug Mode 238
bus timing 70
BUSACK 9, 70, 239, 249, 255, 355
BUSACK pin 89, 249, 255
BUSREQ 9, 70, 255
BUSREQ pin 89, 239, 249, 255
Byte Format, I2C 213
C
C source-level debugging 231
capture flag 128
Carrier Sense 307
carrier sense 303
carrier sense window 308
Carrier Sense Window Referencing 308
Carrier Sense, MII 22
Chain Sequence and Length, JTAG Boundary Scan
260
Characteristics, electrical
Charge Pump 265
charge pump 269
Charge Pump, PLL 266
Chip Select Registers 85
Chip Select x Bus Mode Control Register 88
Chip Select x Control Register 87
Chip Select x Lower Bound Register 85
Chip Select x Upper Bound Register 86
Chip Select/Wait State Generator block 6
Chip Selects During Bus Request/Bus Acknowl-
edge Cycles 70
Clear to Send 12, 15, 193
CLK_MUX 269
clock divisor value, 16-bit 182, 206
clock initialization circuitry 258
Clock Peripheral Power-Down Registers 46
clock phase 202
clock phase bit 204
PS019215-0910
Absolute maximum ratings 339
clock polarity bit 204
Clock Synchronization for Handshake 216
Clock Synchronization, I2C 214
Clocking Overview 211
COL 22
Complex triggers 257
CONTINUOUS mode 125
Continuous Mode 123, 126
continuous mode 121, 132, 138, 139
Control Transfers, UART 179
CPHA—see clock phase 202, 203, 208
CPOL—see clock polarity 203, 208
CRC 294, 295, 299, 300, 312
CRS 22, 307
CS0 7, 65, 66, 67, 68
CS1 7, 65, 66, 67, 68
CS2 7, 65, 67, 68
CS3 7, 65, 67, 68
CTS 191, 193
CTS0 12, 198
CTS1 15
Customer Feedback Form 375
D
DATA bus 78
Data Bus 8
data bus 70, 71, 73, 74, 75, 82, 88, 161, 238,
239, 249, 255
Data Carrier Detect 13, 16, 193
Data Set Ready 13, 16, 193
Data Terminal Ready 12, 15, 191
Data Transfer Procedure with SPI configured as a
Slave 206
Data Transfer Procedure with SPI Configured as the
Master 205
data transfer, SPI 209
Data Transfers, UART 179
Data Validity, I2C 212
DATA0 8
DATA1 8
DATA2 8
DATA3 8
DATA4 8
Product Specification
Index
362