EZ80F91NA050SC Zilog, EZ80F91NA050SC Datasheet - Page 212

• Manufacturer Part Number: EZ80F91NA050SC
• Description: IC ACCLAIM MCU 256KB 144-BGA
• Manufacturer: Zilog
• Series: eZ80® Acclaim!®r

Specifications of EZ80F91NA050SC

• Core Processor: Z8
• Core Size: 8-Bit
• Speed: 50MHz
• Connectivity: Ethernet, I²C, IrDA, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 32
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Oscillator Type: Internal
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 144-LBGA
• Data Bus Width: 8 bit
• Maximum Clock Frequency: 50 MHz
• Data Ram Size: 16 KB
• Number Of Programmable I/os: 32
• Number Of Timers: 16 Bit
• Operating Supply Voltage: 3 V to 3.6 V
• Mounting Style: SMD/SMT
• Height: 1.5 mm
• Length: 13 mm
• Maximum Operating Temperature: + 70 C
• Minimum Operating Temperature: 0 C
• Width: 13 mm
• For Use With: 269-4712 - KIT DEV ENCORE 32 SERIES269-4671 - BOARD ZDOTS SBC Z80ACCLAIM PLUS269-4561 - KIT DEV FOR EZ80F91 W/C-COMPILER269-4560 - KIT DEV FOR EZ80F91 W/C-COMPILER
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: No RoHS Version Available
• Other names: 269-3251

Table 111. SPI Clock Phase and Clock Polarity Operation
PS019215-0910
CPHA
(CPHA bit = 0) Data Out
(CPHA bit = 1) Data Out
0
0
1
1
ENABLE (To Slave)
SCK (CPOL bit = 0)
SCK (CPOL bit = 1)
Sample Input
Sample Input
CPOL
divide-by-two clock divider. In MASTER mode, the SPI serial clock is one-half the fre-
quency of the clock signal created by the SPI’s Baud Rate Generator.
As displayed in
using the clock polarity (CPOL) and clock phase CPHA control bits in the SPI Control
register. See
with the identical timing, CPOL, and CPHA. The master device always places data on the
MOSI line a half-cycle before the clock edge (SCK signal), for the slave device to latch
the data.
0
1
0
1
Transmit
SPI Control Register
Falling
Falling
Rising
Rising
Edge
SCK
Figure 42
MSB
MSB
1
SCK
Receive
Edge
Figure 42. SPI Timing
6
and
Falling
Falling
Rising
Rising
6
2
Table
Number of Cycles on the SCK Signal
5
on page 208. Both the master and slave must operate
111, four possible timing relations are chosen by
5
3
4
State
SCK
High
High
Low
Low
Idle
4
4
3
3
5
Characters?
2
Between
SS High
Yes
Yes
No
No
2
6
Product Specification
1
Serial Peripheral Interface
1
7
LSB
eZ80F91 MCU
LSB
8
203