EZ80F91NA050SC Zilog, EZ80F91NA050SC Datasheet - Page 307

• Manufacturer Part Number: EZ80F91NA050SC
• Description: IC ACCLAIM MCU 256KB 144-BGA
• Manufacturer: Zilog
• Series: eZ80® Acclaim!®r

Specifications of EZ80F91NA050SC

• Core Processor: Z8
• Core Size: 8-Bit
• Speed: 50MHz
• Connectivity: Ethernet, I²C, IrDA, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 32
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Oscillator Type: Internal
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 144-LBGA
• Data Bus Width: 8 bit
• Maximum Clock Frequency: 50 MHz
• Data Ram Size: 16 KB
• Number Of Programmable I/os: 32
• Number Of Timers: 16 Bit
• Operating Supply Voltage: 3 V to 3.6 V
• Mounting Style: SMD/SMT
• Height: 1.5 mm
• Length: 13 mm
• Maximum Operating Temperature: + 70 C
• Minimum Operating Temperature: 0 C
• Width: 13 mm
• For Use With: 269-4712 - KIT DEV ENCORE 32 SERIES269-4671 - BOARD ZDOTS SBC Z80ACCLAIM PLUS269-4561 - KIT DEV FOR EZ80F91 W/C-COMPILER269-4560 - KIT DEV FOR EZ80F91 W/C-COMPILER
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: No RoHS Version Available
• Other names: 269-3251

Table 180. EMAC Test Register
PS019215-0910
Bit
Reset
CPU Access
Note: R/W = Read/Write, R = Read Only.
Bit 
Position
7
6
TEST_FIFO
5
TxRx_SEL
4
SSTC
3
SIMR
2
FRC_OVR_ERR
1
FRC_UND_ERR
0
LPBK
EMAC Test Register
The EMAC Test Register allows test functionality of the EMAC block. Available test
modes are defined for bits [6:0]. See
Value
0
0
1
0
1
0
1
0
1
0
1
0
1
0
1
R
7
0
Description
Reserved.
FIFO test mode disabled—Normal operation.
FIFO test mode enabled.
Select the Receive FIFO when FIFO test mode is enabled.
Select the Transmit FIFO when FIFO test mode is enabled.
Normal operation.
Short Cut Slot Timer Counter. Slot time is shortened to
speed up simulation.
Normal operation.
Simulation Reset.
Normal operation.
Force Overrun error in Receive FIFO.
Normal operation.
Force Underrun error in Transmit FIFO.
Normal operation.
EMAC Transmit interface is looped back into EMAC Receive
interface.
R/W
6
0
(EMAC_ TEST = 0020h)
R/W
5
0
R/W
4
0
Table
R/W
180.
3
0
R/W
2
0
R/W
Ethernet Media Access Controller
1
0
Product Specification
R/W
0
0
298