EZ80F91NA050SC Zilog, EZ80F91NA050SC Datasheet - Page 338

• Manufacturer Part Number: EZ80F91NA050SC
• Description: IC ACCLAIM MCU 256KB 144-BGA
• Manufacturer: Zilog
• Series: eZ80® Acclaim!®r

Specifications of EZ80F91NA050SC

• Core Processor: Z8
• Core Size: 8-Bit
• Speed: 50MHz
• Connectivity: Ethernet, I²C, IrDA, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 32
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Oscillator Type: Internal
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 144-LBGA
• Data Bus Width: 8 bit
• Maximum Clock Frequency: 50 MHz
• Data Ram Size: 16 KB
• Number Of Programmable I/os: 32
• Number Of Timers: 16 Bit
• Operating Supply Voltage: 3 V to 3.6 V
• Mounting Style: SMD/SMT
• Height: 1.5 mm
• Length: 13 mm
• Maximum Operating Temperature: + 70 C
• Minimum Operating Temperature: 0 C
• Width: 13 mm
• For Use With: 269-4712 - KIT DEV ENCORE 32 SERIES269-4671 - BOARD ZDOTS SBC Z80ACCLAIM PLUS269-4561 - KIT DEV FOR EZ80F91 W/C-COMPILER269-4560 - KIT DEV FOR EZ80F91 W/C-COMPILER
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: No RoHS Version Available
• Other names: 269-3251

Table 221. EMAC Receive Write Pointer Register—High Byte
Table 222. EMAC Transmit Read Pointer Register—Low Byte
PS019215-0910
Bit
Reset
CPU Access
Note: R = Read Only.
Bit 
Position
[7:0]
EMAC_RWP_H
Bit
Reset
CPU Access
Note: R = Read Only.
Bit 
Position
[7:0]
EMAC_TRP_L
EMAC Receive Write Pointer Register—High Byte
Because of the size of the EMAC’s 8 KB SRAM, the upper three bits of the EMAC
Receive Write Pointer Register are always zero.
EMAC Transmit Read Pointer Register—Low Byte
The Low byte of the Transmit Read Pointer register reports the current TxDMA Transmit
Read pointer.This pointer is initialized to EmacTLBP whenever Emac_RST bits SRST or
HRRTN are set. Because the size of the packet is limited to a minimum of 32 bytes, the
last five bits are always zero. See
Value
00h–E0h These bits represent the Low byte of the 2 byte EMAC
Value
00h–1Fh These bits represent the High byte of the 2 byte EMAC
R
R
7
0
7
0
Description
TxDMA
EMAC_TRP_L}. Bit 7 is bit 7 of the 16 bit value. Bit 0 is bit 0
(lsb) of the 16 bit value.
Description
RxDMA Receive Write Pointer value, {EMAC_RWP_H,
EMAC_RWP_L}. Bit 7 is bit 15 (msb) of the 16 bit value. Bit
0 is bit 8 of the 16 bit value.
R
R
6
0
6
0
Transmit Read Pointer
R
R
5
0
5
0
Table
R
R
4
0
4
0
222.
R
R
3
0
3
0
value, {EMAC_TRP_H,
R
R
2
0
2
0
(EMAC_RWP_H = 0052h)
(EMAC_TRP_L = 0053h)
Ethernet Media Access Controller
R
R
1
0
1
0
Product Specification
R
R
0
0
0
0
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