EZ80F91NA050SC Zilog, EZ80F91NA050SC Datasheet - Page 55

IC ACCLAIM MCU 256KB 144-BGA

EZ80F91NA050SC

Manufacturer Part Number
EZ80F91NA050SC
Description
IC ACCLAIM MCU 256KB 144-BGA
Manufacturer
Zilog
Series
eZ80® Acclaim!®r
Datasheets

Specifications of EZ80F91NA050SC

Core Processor
Z8
Core Size
8-Bit
Speed
50MHz
Connectivity
Ethernet, I²C, IrDA, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
32
Program Memory Size
256KB (256K x 8)
Program Memory Type
FLASH
Ram Size
16K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Oscillator Type
Internal
Operating Temperature
0°C ~ 70°C
Package / Case
144-LBGA
Data Bus Width
8 bit
Maximum Clock Frequency
50 MHz
Data Ram Size
16 KB
Number Of Programmable I/os
32
Number Of Timers
16 Bit
Operating Supply Voltage
3 V to 3.6 V
Mounting Style
SMD/SMT
Height
1.5 mm
Length
13 mm
Maximum Operating Temperature
+ 70 C
Minimum Operating Temperature
0 C
Width
13 mm
For Use With
269-4712 - KIT DEV ENCORE 32 SERIES269-4671 - BOARD ZDOTS SBC Z80ACCLAIM PLUS269-4561 - KIT DEV FOR EZ80F91 W/C-COMPILER269-4560 - KIT DEV FOR EZ80F91 W/C-COMPILER
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Eeprom Size
-
Data Converters
-
Lead Free Status / Rohs Status
No RoHS Version Available
Other names
269-3251

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
EZ80F91NA050SC
Manufacturer:
Zilog
Quantity:
10 000
Part Number:
EZ80F91NA050SC00TR
Manufacturer:
Zilog
Quantity:
10 000
PS019215-0910
Clock Peripheral Power-Down Registers
The CPU is brought out of HALT mode by any of the following operations:
To minimize current in HALT mode, the system clock must be gated-off for all unused 
on-chip peripherals via the Clock Peripheral Power-Down Registers.
HALT Mode and the EMAC Function
When the CPU is in HALT mode, the eZ80F91 device’s EMAC block cannot be disabled
as other peripherals can. On receipt of an Ethernet packet, a maskable Receive interrupt is
generated by the EMAC block, just as it would be in a non-halt mode. Accordingly, the
processor wakes up and continues with the user-defined application.
To reduce power, the Clock Peripheral Power-Down Registers allow the system clock to
be blocked to unused on-chip peripherals. On RESET, all peripherals are enabled. The
clock to unused peripherals are gated off by setting the appropriate bit in the Clock Periph-
eral Power-Down Registers to 1. When powered down, the peripherals are completely dis-
abled. To re-enable, the bit in the Clock Peripheral Power-Down Registers must be cleared
to 0.
Additionally, the VBO_OFF bit of CLK_PPD2 is used to disable the VBO detection cir-
cuit and thereby significantly reduce DC current consumption (see
when this function is not required.
Many peripherals features separate enable/disable control bits that must be appropriately
set for operation. These peripheral specific enable/disable bits do not provide the same
level of power reduction as the Clock Peripheral Power-Down Registers. When powered
down, the individual peripheral control register is not accessible for Read or Write access,
(see
The PC stops incrementing.
A nonmaskable interrupt (NMI).
A maskable interrupt.
A RESET via the external RESET pin driven Low.
A Watchdog Timer time-out (if, configured to generate either an NMI or RESET upon
time-out).
A RESET via execution of a Debug RESET command.
A RESET via the Low-Voltage Brownout detection circuit, if enabled.
Table 4
on page 47 and
Table 5
on page 48).
Product Specification
Table 234
Low-Power Modes
on page 341)
46

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