EZ80F91NA050SC Zilog, EZ80F91NA050SC Datasheet - Page 15

• Manufacturer Part Number: EZ80F91NA050SC
• Description: IC ACCLAIM MCU 256KB 144-BGA
• Manufacturer: Zilog
• Series: eZ80® Acclaim!®r

Specifications of EZ80F91NA050SC

• Core Processor: Z8
• Core Size: 8-Bit
• Speed: 50MHz
• Connectivity: Ethernet, I²C, IrDA, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 32
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Oscillator Type: Internal
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 144-LBGA
• Data Bus Width: 8 bit
• Maximum Clock Frequency: 50 MHz
• Data Ram Size: 16 KB
• Number Of Programmable I/os: 32
• Number Of Timers: 16 Bit
• Operating Supply Voltage: 3 V to 3.6 V
• Mounting Style: SMD/SMT
• Height: 1.5 mm
• Length: 13 mm
• Maximum Operating Temperature: + 70 C
• Minimum Operating Temperature: 0 C
• Width: 13 mm
• For Use With: 269-4712 - KIT DEV ENCORE 32 SERIES269-4671 - BOARD ZDOTS SBC Z80ACCLAIM PLUS269-4561 - KIT DEV FOR EZ80F91 W/C-COMPILER269-4560 - KIT DEV FOR EZ80F91 W/C-COMPILER
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: No RoHS Version Available
• Other names: 269-3251

PS019215-0910
Table 2. Pin Identification on the eZ80F91 Device
LQFP
Pin No
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
Pin Characteristics
BGA
Pin No Symbol
A1
B1
B2
C3
D4
C1
C2
E5
D2
D1
D3
F6
E1
E2
E3
E4
Table 2
144-BGA package.
ADDR0
ADDR1
ADDR2
ADDR3
ADDR4
V
V
ADDR5
ADDR6
ADDR7
ADDR8
ADDR9
ADDR10
V
V
ADDR11
DD
SS
DD
SS
lists the pins and functions of the eZ80F91 MCU’s 144-pin LQFP package and
Function
Address Bus
Address Bus
Address Bus
Address Bus
Address Bus
Power Supply
Ground
Address Bus
Address Bus
Address Bus
Address Bus
Address Bus
Address Bus
Power Supply
Ground
Address Bus
Signal Direction Description
Bidirectional
Bidirectional
Bidirectional
Bidirectional
Bidirectional
Bidirectional
Bidirectional
Bidirectional
Bidirectional
Bidirectional
Bidirectional
Bidirectional
Configured as an output in normal
operation. The address bus selects a
location in memory or I/O space to be
read or written. Configured as an input
during bus acknowledge cycles.
Drives the Chip Select/Wait State
Generator block to generate Chip
Selects.
Power Supply.
Ground.
Configured as an output in normal
operation. The address bus selects a
location in memory or I/O space to be
read or written. Configured as an input
during bus acknowledge cycles.
Drives the Chip Select/Wait State
Generator block to generate Chip
Selects.
Power Supply.
Ground.
Configured as an output in normal
operation. The address bus selects a
location in memory or I/O space to be
read or written. Configured as an input
during bus acknowledge cycles.
Drives the Chip Select/Wait State
Generator block to generate Chip
Selects.
Product Specification
Architectural Overview
6