EZ80F91NA050SC Zilog, EZ80F91NA050SC Datasheet - Page 59

• Manufacturer Part Number: EZ80F91NA050SC
• Description: IC ACCLAIM MCU 256KB 144-BGA
• Manufacturer: Zilog
• Series: eZ80® Acclaim!®r

Specifications of EZ80F91NA050SC

• Core Processor: Z8
• Core Size: 8-Bit
• Speed: 50MHz
• Connectivity: Ethernet, I²C, IrDA, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 32
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Oscillator Type: Internal
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 144-LBGA
• Data Bus Width: 8 bit
• Maximum Clock Frequency: 50 MHz
• Data Ram Size: 16 KB
• Number Of Programmable I/os: 32
• Number Of Timers: 16 Bit
• Operating Supply Voltage: 3 V to 3.6 V
• Mounting Style: SMD/SMT
• Height: 1.5 mm
• Length: 13 mm
• Maximum Operating Temperature: + 70 C
• Minimum Operating Temperature: 0 C
• Width: 13 mm
• For Use With: 269-4712 - KIT DEV ENCORE 32 SERIES269-4671 - BOARD ZDOTS SBC Z80ACCLAIM PLUS269-4561 - KIT DEV FOR EZ80F91 W/C-COMPILER269-4560 - KIT DEV FOR EZ80F91 W/C-COMPILER
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: No RoHS Version Available
• Other names: 269-3251

Table 6. GPIO Mode Selection
PS019215-0910
GPIO
Mode
1
2
3
4
5
6
7
8
9
Px_ALT2
Bits7:0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
Figure 5
GPIO port pin for the various modes.
GPIO Mode 1—Output
The port pin is configured as a standard digital output pin. The value written to the Port x
Data register (Px_DR) is driven on the pin.
GPIO Mode 2—Input
The port pin is configured as a standard digital input pin. The output is high impedance.
The value stored in the Port x Data register produces no effect. As in all modes, a read
from the Port x Data register returns the pin’s value. GPIO mode 2 is the default operating
mode following a RESET.
GPIO Mode 3—Open Drain
The port pin is configured as open-drain Input/Output. The GPIO pins do not feature an
internal pull-up to the supply voltage. To employ the GPIO pin in OPEN-DRAIN mode,
Px_ALT1
Bits7:0
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
on page 53 and
Px_DDR
Bits7:0
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
Bits7:0 Port Mode
Px_DR
Figure 6
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
Output
Output
Input from pin
Input from pin
Open-drain output
Open-drain I/O
Open-source I/O
Open-source output
Reserved
Interrupt—dual edge-triggered
Alternate function controls port I/O.
Alternate function controls port I/O.
Interrupt—active Low
Interrupt—active High
Interrupt—falling edge-triggered
Interrupt—rising edge-triggered
on page 53 display the simplified block diagrams of the
General-Purpose Input/Output
Product Specification
0
1
High impedance
High impedance
0
High impedance
High impedance
1
High impedance
High impedance
Output
High impedance
High impedance
High impedance
High impedance
eZ80F91 MCU
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